User:Lidnariq/Discrete Logic Table

It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.

GxROM-like		8kB CHR bank bits
		0	1	2	3	4	5	6	7	8
32kB PRG bank bits	0	NROM	Vs. System	CNROM, 87, 101, CPROM†						oversize CNROM
	1	AN1ROM¹		MHROM	NINA-03/06
	2	ANROM¹, BNROM		GNROM, 38	58ʰ, 86, 96†, 174ʰ	11, 36, 57ʰ, 140		oversize 38
	3	AOROM¹				113ʰ
	4	oversize AxROM¹, 231ʰ				oversize GNROM
	5								46
	6	226ʰ						228ʰ	62ʰ
	7
	8	oversize BNROM

UxROM-like		8kB CHR bank bits
		0	1	2	3	4	5	6
16kB PRG bank bits	2					168†
	3	UNROM, 94, 180		29		72, 78¹­ʰ, 89¹, 93*, 152¹
	4	UOROM				70, 92
	5			Sealie UNROM 512¹
	6	oversize 94
	7
	8	oversize UxROM, oversize 180

† 4F+4 or 4+4F CHR-RAM banking, not 8 CHR-ROM banking
¹ has mapper-controlled single-screen mirroring
ʰ has mapper-controlled H/V mirroring
* Emulators commonly implement mapper 93 as a plain UNROM variant, not supporting CHR banking. But the hardware does support it.

Non-standard CHR banking:

• NINA-001 has 1 bit for 32 PRG and 8 bits for 4+4 CHR banking
• 77 has 4 bits for 2+6R CHR banking (plus 4 bits for 32 PRG banking)
• 60, 107, and 201 use the same bits to control both PRG and CHR banks
• 184 has 5 bits for 4+4 CHR banking