User contributions for Lidnariq
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29 November 2024
- 16:0816:08, 29 November 2024 diff hist +324 Jaleco SS 88006 pinout audio circuit, only nontrivial because µPD775X needs an external pullup current
22 November 2024
- 16:2516:25, 22 November 2024 diff hist +20 m GTROM jordigh asked for an account to add this so i added this
15 November 2024
- 11:5911:59, 15 November 2024 diff hist +27 m MMC5 →Read: fix link current
2 November 2024
- 13:0813:08, 2 November 2024 diff hist +18 m Jaleco SS 88006 pinout 256KiB games have to have a trace for PRG A17...
1 November 2024
- 17:2417:24, 1 November 2024 diff hist +146 Jaleco SS 88006 pinout misleading bit about under what circumstances M2 and /ROMSEL are delayed (in practice, never)
30 October 2024
- 18:4218:42, 30 October 2024 diff hist 0 Jaleco SS 88006 pinout oscillator pin directions are knowable from the datasheet
- 14:3914:39, 30 October 2024 diff hist +506 VRC7 audio →Debug Mode: Rhythm register meaningfully exists when in debug mode, so add documentation current
27 October 2024
- 16:4716:47, 27 October 2024 diff hist +61 PT8159 Pinout include source for xref
10 October 2024
- 10:3910:39, 10 October 2024 diff hist 0 MMC4 pinout we don't use the word "unknown" on pinouts
6 October 2024
- 11:3611:36, 6 October 2024 diff hist −161 VRC7 Undo revision 22101 by PizzerLover123 (talk) this really doesn't belong here current Tag: Undo
23 September 2024
- 20:4020:40, 23 September 2024 diff hist +124 MMC1 →Control (internal, $8000-$9FFF): use 'arrangement' terminology for nametable control
19 September 2024
- 09:1609:16, 19 September 2024 diff hist +66 CPU variants →Unofficial: previous edit made a mess of the multi-part description of the UA6527P; split it into four rows to fix that
- 09:0909:09, 19 September 2024 diff hist −42 CPU variants 2A04 shouldn't really be off at the bottom all by itself; while it's technically neither NTSC or PAL nor Clone, it was used in place of NTSC CPUs so put it in that section
9 September 2024
- 19:2819:28, 9 September 2024 diff hist 0 m Controller port pinout →Pinout: typo current
- 16:3716:37, 9 September 2024 diff hist 0 PPU variants →PAL: my 2C07-0 is even later
8 September 2024
- 10:5610:56, 8 September 2024 diff hist +352 Cartridge connector →Pinout of 60-pin Famicom consoles and cartridges current
7 September 2024
- 16:3016:30, 7 September 2024 diff hist +42 INES Mapper 246 →PRG-ROM bank select ($6000-$6003), write: it's 16 specific addresses, not the 28 byte region current
28 August 2024
- 07:2407:24, 28 August 2024 diff hist 0 INES Mapper 246 →PRG-ROM bank select ($6000-$6003), write: Nothing can reset the state of the 74'670; it's only an emergent property - not even part of the specification - that it powers up holding all $FF
27 August 2024
- 08:3608:36, 27 August 2024 diff hist +83 INES Mapper 246 alternative hypothesis for the existing dumps
- 07:0307:03, 27 August 2024 diff hist +50 INES Mapper 246 ellipsis is confusing apparently
26 August 2024
- 19:3619:36, 26 August 2024 diff hist −2 m Cycle reference chart →Clock rates: someone found "every other" insufficiently clear current
19 August 2024
- 07:4707:47, 19 August 2024 diff hist +33 MK5060 pinout official PCE PAL didn't use MK5060 current
16 August 2024
- 07:5307:53, 16 August 2024 diff hist +95 Namcot 163 family pinout SCSR's die tracing findings current
- 07:3007:30, 16 August 2024 diff hist −1 m INES Mapper 019 →PRG Select 3 ($F000-$F7FF) w: rephase current
- 07:3007:30, 16 August 2024 diff hist +114 INES Mapper 019 →PRG Select 3 ($F000-$F7FF) w: SCSR found pin 44 is something weirder
26 July 2024
- 15:2815:28, 26 July 2024 diff hist +3 m Mask ROM pinout →Nintendo RROM CHR ROM pinout - 8 KBytes (28pin): bootgod's gone current
18 July 2024
- 09:5609:56, 18 July 2024 diff hist +26 N User:Lidnariq/PPU glitches Lidnariq moved page User:Lidnariq/PPU glitches to PPU glitches: requested promotion out of my user space current Tag: New redirect
- 09:5609:56, 18 July 2024 diff hist 0 m PPU glitches Lidnariq moved page User:Lidnariq/PPU glitches to PPU glitches: requested promotion out of my user space
8 July 2024
- 19:5519:55, 8 July 2024 diff hist +120 CPU variants there was a ua6547??
- 19:5519:55, 8 July 2024 diff hist +73 N File:CPU=UA6547 8950S.JPG from chirinea with permission current
27 June 2024
- 07:4307:43, 27 June 2024 diff hist +1 m INES Mapper 240 crlf current
- 07:4307:43, 27 June 2024 diff hist +295 INES Mapper 240 some mapper details from NewRisingSun
18 June 2024
- 16:4416:44, 18 June 2024 diff hist +73 INES Mapper 148 someone bothered to trace the photos in the flickr link and found that CPU A13 and A14 are also ORed into the bits that must not be set for a mapper write current
- 08:1208:12, 18 June 2024 diff hist +360 File:CPU=RP2A03G 8K5 81.jpg →Date stamps seen: add loglow's data from the forum current
17 June 2024
- 07:2607:26, 17 June 2024 diff hist +23 m File:CPU=RP2A03E VF4109 5H4 8582.jpg →Date stamps seen: and the depicted one current
- 07:2607:26, 17 June 2024 diff hist +283 File:CPU=RP2A03E VF4109 5H4 8582.jpg a bunch of datestamps
4 June 2024
- 17:0017:00, 4 June 2024 diff hist +9 IRQ $4015 writes to acknowledge the DMC IRQ, as seen in visual2a03. (see t14787) current
23 May 2024
- 21:5821:58, 23 May 2024 diff hist +17 RP2C33 pinout pins 61, 53, and 24 were determined experimentally on the discord. current
13 May 2024
- 18:5818:58, 13 May 2024 diff hist +96 PPU variants explain what "particularly susceptible to reflections" means
7 April 2024
- 14:2814:28, 7 April 2024 diff hist −225 CPU variants eugene-s tells me that all four revisions of the 6561xx-2s as well as 6561F-1 have the correct duty cycles, and that revision F is oldest, so it's unlikely that QFP80 6561 duties were ever wrong
- 07:3307:33, 7 April 2024 diff hist +1 Cycle reference chart →Clock rates: braino
- 07:2607:26, 7 April 2024 diff hist +8 m Cycle reference chart put back dendy name
25 March 2024
- 12:3912:39, 25 March 2024 diff hist +36 RP2C33 pinout switch to webarchive for electronics junker's schematic
20 March 2024
- 08:4108:41, 20 March 2024 diff hist −157 CPU power up state →At power-up: P is not 8 bits wide. Don't define the other two bits because they don't exist.
12 March 2024
- 08:3508:35, 12 March 2024 diff hist +49 m Cycle reference chart →Clock rates: specify what "unknown" means for the brazil famiclone
10 March 2024
- 17:1917:19, 10 March 2024 diff hist +100 PPU scrolling →The common case: make scroll coordinate packing a little more explicit
9 March 2024
- 14:5314:53, 9 March 2024 diff hist +45 Cycle reference chart →Clock rates: collapse the RGB PPUs into one column and add the PAL-M/N famiclones to the lineup. And this is still missing the SECAM famiclone and HK NES
7 March 2024
- 16:0516:05, 7 March 2024 diff hist +58 MC-ACC pinout pin 39 confirmed; bootgod link moved to nescartdb link current
6 March 2024
- 09:1309:13, 6 March 2024 diff hist −2 m User:Lidnariq/NES-21G-CPU-72P when will i stop thinking Fujitsu's F̲̅ chip logo is Fairchild's?? current
24 February 2024
- 07:5607:56, 24 February 2024 diff hist −2 m INES Mapper 033 fix link current
