INES Mapper 201: Difference between revisions

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(look through goodnes for m201 games for number of bits in register)
(Executive summary)
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[[Category:iNES Mappers|201]][[Category:Multicart mappers|201]]
[[Category:iNES Mappers|201]][[Category:Multicart mappers|201]]
'''iNES Mapper 201''' has been assigned to a multicart mapper designed to contain multiple NROM-256 games.
It acts like [[BNROM]] and [[CNROM]] overlaid: one bank number controls both 32 KiB PRG banks and 8 KiB CHR banks.
   Here are Disch's original notes:   
   Here are Disch's original notes:   
   ========================
   ========================
Line 36: Line 39:
       +-------------------------------+
       +-------------------------------+


There are almost assuredly only 2 bits in the above register (all known games are 128KiB PRG / 32KiB CHR)
All known games on this mapper use only the two least significant bits (128KiB PRG / 32KiB CHR).

Revision as of 19:40, 13 May 2013

iNES Mapper 201 has been assigned to a multicart mapper designed to contain multiple NROM-256 games. It acts like BNROM and CNROM overlaid: one bank number controls both 32 KiB PRG banks and 8 KiB CHR banks.

 Here are Disch's original notes:  
 ========================
 =  Mapper 201          =
 ========================
 
 Example Games:
 --------------------------
 8-in-1
 21-in-1 (2006-CA) (Unl)
 
 
 Registers:
 ---------------------------
 
 
   $8000-FFFF:  A~[.... ....  RRRR RRRR]
     R = PRG/CHR Reg
 
 
 CHR Setup:
 ---------------------------
 
       $0000   $0400   $0800   $0C00   $1000   $1400   $1800   $1C00 
     +---------------------------------------------------------------+
     |                             $8000                             |
     +---------------------------------------------------------------+
 
 
 PRG Setup:
 ---------------------------
 
      $8000   $A000   $C000   $E000  
     +-------------------------------+
     |             $8000             |
     +-------------------------------+

All known games on this mapper use only the two least significant bits (128KiB PRG / 32KiB CHR).