Comparison of Nintendo mappers: Difference between revisions
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| [[INES Mapper 119|119]] || MMC3 || [[TQROM]] || 128 || 8 + 8 + 16F || 64 + 8 || 2 + 2 + 1 + 1 + 1 + 1 || V/H switchable || No || Scanline IRQ | | [[INES Mapper 119|119]] || MMC3 || [[TQROM]] || 128 || 8 + 8 + 16F || 64 + 8 || 2 + 2 + 1 + 1 + 1 + 1 || V/H switchable || No || Scanline IRQ | ||
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| 4 || [[MMC6]] || [[HKROM]] || 512 || 8 + 8 + 16F || 256 || 2 + 2 + 1 + 1 + 1 + 1 || V/H switchable || 1KiB built-in || Scanline IRQ | |||
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| [[iNES Mapper 005|5]] || [[MMC5]] || [[ExROM]] || 1024 || 32, 16 + 16, 16 + 8 + 8, 8 + 8 + 8 + 8 || 1024 || BG: 4, 2 + 2, or 1 + 1 + 1 + 1<br>Sprites: 8, 4 + 4, 2 * 4, or 1 * 8<br>Split window: 4 || Any || 1 KiB built in; more optional || Scanline IRQ<br>Smaller attribute areas<br>Separate CHR bank per background tile<br>Separate sets of CHR banks for sprites<br>Vertical split screen<br>8x8 multiplier | | [[iNES Mapper 005|5]] || [[MMC5]] || [[ExROM]] || 1024 || 32, 16 + 16, 16 + 8 + 8, 8 + 8 + 8 + 8 || 1024 || BG: 4, 2 + 2, or 1 + 1 + 1 + 1<br>Sprites: 8, 4 + 4, 2 * 4, or 1 * 8<br>Split window: 4 || Any || 1 KiB built in; more optional || Scanline IRQ<br>Smaller attribute areas<br>Separate CHR bank per background tile<br>Separate sets of CHR banks for sprites<br>Vertical split screen<br>8x8 multiplier | ||
Revision as of 19:50, 28 June 2012
This article compares the capabilities of several Nintendo mappers.
Discrete logic
All of Nintendo's discrete logic mappers have bus conflicts except some revisions of 7.
| iNES | Chips | Boards | Max PRG | PRG banks | Max CHR | CHR banks | Mirroring | PRG RAM? | IRQ |
|---|---|---|---|---|---|---|---|---|---|
| 0 | 0-1 | NROM | 32 | 8 | V/H hardwired | Rare | None | ||
| 2 | 2 | UNROM, UOROM | 256 | 16 + 16F | 8 | V/H hardwired | No | None | |
| 3 | 1 | CNROM | 32 | 32 | 8 | V/H hardwired | No | None | |
| 7 | 1-2 | AxROM | 256 | 32 | 8 | 1 | No | None | |
| 13 | 1 | CPROM (U) | 32 | 16 | 4 + 4F | V/H hardwired | No | None | |
| 34 | 1 | BNROM | 256 | 32 | 8 | V/H hardwired | No | None | |
| 66 | 1 | GNROM, MHROM | 128 | 32 | 32 | 8 | V/H hardwired | No | None |
| 180 | 2 | UNROM | 256 | 16F + 16 | 8 | V/H hardwired | No | None |
ASIC
None of these ASIC mappers has bus conflicts.
| iNES | Mapper | Boards | Max PRG ROM | PRG ROM banks | Max CHR | CHR banks | Mirroring | PRG RAM? | Assist |
|---|---|---|---|---|---|---|---|---|---|
| 1 | MMC1 | SGROM, SNROM, SUROM | 512 | 16 + 16F; 32 | 8 | 4 + 4 | V/H/1 switchable | Optional | None |
| 1 | MMC1 | SKROM, SLROM | 256 | 16 + 16F; 32 | 128 | 4 + 4 | V/H/1 switchable | Optional | None |
| 4 | MMC3 | TxROM | 512 | 8 + 8 + 16F | 256 | 2 + 2 + 1 + 1 + 1 + 1 | V/H switchable | Optional | Scanline IRQ |
| 4 | MMC3 | TGROM, TNROM | 512 | 8 + 8 + 16F | 8 | 2 + 2 + 1 + 1 + 1 + 1 | V/H switchable | Japan only | Scanline IRQ |
| 118 | MMC3 | TKSROM, TLSROM | 512 | 8 + 8 + 16F | 128 | 2 + 2 + 1 + 1 + 1 + 1 | Any switchable | Optional | Scanline IRQ |
| 119 | MMC3 | TQROM | 128 | 8 + 8 + 16F | 64 + 8 | 2 + 2 + 1 + 1 + 1 + 1 | V/H switchable | No | Scanline IRQ |
| 4 | MMC6 | HKROM | 512 | 8 + 8 + 16F | 256 | 2 + 2 + 1 + 1 + 1 + 1 | V/H switchable | 1KiB built-in | Scanline IRQ |
| 5 | MMC5 | ExROM | 1024 | 32, 16 + 16, 16 + 8 + 8, 8 + 8 + 8 + 8 | 1024 | BG: 4, 2 + 2, or 1 + 1 + 1 + 1 Sprites: 8, 4 + 4, 2 * 4, or 1 * 8 Split window: 4 |
Any | 1 KiB built in; more optional | Scanline IRQ Smaller attribute areas Separate CHR bank per background tile Separate sets of CHR banks for sprites Vertical split screen 8x8 multiplier |
| 9 | MMC2 | PNROM | 128 | 8 + 24F | 128 | 4/4 + 4/4 | V/H switchable | No | Tile triggered CHR bank switching |
| 10 | MMC4 | FJROM, FKROM (J) | 256 | 16 + 16F | 128 | 4/4 + 4/4 | V/H switchable | Yes | Tile triggered CHR bank switching |
External links
- Mapper wizard: Web-based decision tree for choosing a mapper for your NES project
