User:Zzo38/Mapper E

This is a mapper for multigame cartridges, although it has other features useful for other purposes, too. Compare also iNES Mapper 028.

You may be able to make multiple programs using mappers such as:

• NROM
• CNROM (with no expansion audio, although security diodes are possible)
• GNROM
• UNROM
• UxROM
• AxROM
• BNROM
• MHROM
• iNES Mapper 029
• iNES Mapper 038
• iNES Mapper 070
• iNES Mapper 087
• iNES Mapper 092 (you need to provide copies of each bank)
• UN1ROM
• iNES Mapper 101
• iNES Mapper 107
• iNES Mapper 140
• iNES Mapper 203 (16K ROM must be duplicated in ROM image)
• iNES Mapper 218 (all configurations)
• Color Dreams

Depending on ROM/RAM sizes and submapper numbers, it might not be possible to use all combinations.

Registers

Bankswitching masks

[0101 .... .... ..xy]

Writing to these four registers (of eight bits each, regardless of ROM size) controls the bankswitching masks:

• The "x" bit is 0 for PRG banks or 1 for CHR banks (CHR banks can be ROM or RAM; see below section).
• The "y" bit is 0 for AND masks or 1 for XOR masks.

Control register

[0101 .... .... .1..]

Writing to this register will write the control register (one of the mask registers will also be set at the same time).

 7654 3210
[BFUE EEMM]
 |||| ||||
 |||| ||++- Nametable mirroring controls
 |||+-++--- CIRAM enable bits
 ||+------- User register at $6000-$7FFF
 |+-------- Fixed bank at $C000-$FFFF
 +--------- Bus conflicts

The meaning of nametable mirroring controls is determining what CIRAM A10 is connected to:

• 00 = A10
• 01 = A11
• 10 = A12
• 11 = A13

The CIRAM enable bits are as follows (if the bit is set, CIRAM is enabled):

• bit2 = PPU address $0000-$0FFF
• bit3 = PPU address $1000-$1FFF
• bit4 = PPU address $2000-$3FFF

If the control register is exactly $07, and the high four bits of the PRG AND mask are clear, and CHR RAM in the cartridge is enabled, then the CIRAM A10 will be PPU A13 XOR bit4 of the user register.

The user registers at $6000-$7FFF means, if this bit is set, writes to $6000-$FFFF will write the user register; if cleared, the user register is at $8000-$FFFF.

The fixed bank bit, if set, causes reads from $C000-$FFFF to be treated as if the user register is set to $FF, although it doesn't cause it to be changed.

If the bus conflicts bit is set, then there are bus conflicts on registers mapped at $8000-$FFFF. This does not apply to registers mapped at $6000-$7FFF, regardless if this bit is set or not.

User register

The user register is mapped at either $6000-$FFFF or $8000-$FFFF. There is no bus conflicts. Calling the registers "pa" (PRG AND), "px" (PRG XOR), "ca" (CHR AND), "cx" (CHR XOR), and "u" (User), the bank selection is as follows:

• 32K PRG bank at $8000-$FFFF: (u AND pa) XOR px
• 8K CHR bank at $0000-$1FFF and $2000-$3FFF: (u AND ca) XOR cx

If the ROM is small enough that eight bits are not used, the bits of the result are ORed together to determine what bank to select.

Supervisor ROM

Reading from $5000-$5FFF reads from PRG ROM as if the PRG AND mask and PRG XOR mask are both zero (then it will be the same data at $D000-$DFFF).

PRG RAM

There is 8K PRG RAM at $6000-$7FFF (optional feature). Sometimes the user register is also mapped here, but it might not be. There is no bus conflicts.

ROM/RAM sizes

PRG bankswitching is ROM only, although CHR may be ROM and/or RAM. Subtypes of bankswitching are the high two bits of the submapper number for PRG, and the low two bits for CHR.

In the table below, "ROM" and "RAM" means the number of bits needed to select the bank; "-" means the ROM/RAM is not present. The column "sub" means the submapper number.

 ROM   RAM   sub   calc
   0     -     0   No bankswitching
   -     0     0   No bankswitching
   0     0     0   RAM if any bit set; ROM if all bits clear
   1     -     0   Bank 1 if any bit set; bank 0 if all bits clear
   2     -     0   [7531 6420]
   2     -     1   [7654 3210]
   4     -     0   [73 62 51 40]

(TODO)