NES 2.0 submappers

Submapper is a term used in the NES 2.0 header for 4-bit codes designating functionally distinct variants of iNES mappers that cannot be distinguished by the memory size fields alone. Most emulators using iNES format distinguish these using CRC, SHA-1, or other hashes of the PRG ROM and CHR ROM, but this works only for games published prior to 1997, not for fan translations or ROM hacks, and not for new games on the same mapper.

As of early 2012, no submappers were officially defined, but in mid-2012, a drive to collect proposals began. One proposed general principle for backward compatibility is that submapper 0 be reserved for the default iNES behavior.

In September 2012, Kevin Horton finally published a few definitions.

MUST SHOULD MAY

The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this document are to be interpreted as described in RFC 2119. (what's this?)

If value X is "deprecated in favor of" value Y, value X was valid in a previous revision of the submapper spec but is NOT RECOMMENDED anymore. Emulators SHOULD implement them as if they had value Y, and newly released ROM images SHOULD use value Y instead.

001: MMC1

Most MMC1 boards wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner. Boards with CHR RAM wire PRG ROM A18 and the PRG RAM address lines to otherwise unused CHR bank outputs. But among boards designed to take a 32 KiB PRG ROM, some (SIROM) connect PRG ROM A14 to the MMC1's output, others (SEROM, SHROM, SH1ROM) directly to CPU A14.

0: Normal behavior. The PRG ROM size and PRG RAM size determine the function of bits.
1, 2, 4: As 0. Deprecated in favor of 0. (In the Kevtendo, 1 meant SUROM, 2 meant SOROM, and 4 meant SXROM. Since then, the community standardized on using size fields instead.)
3: Treat bit 4 of the PRG bank field as always 0 instead of using it to disable PRG RAM. Deprecated in favor of iNES Mapper 155 so that ROM images stay reasonably compatible with emulators that do not understand NES 2.0.
5: SEROM, SHROM, SH1ROM style: PRG ROM A14 connected directly to CPU A14 (and MMC1 A14 input) instead of MMC1 A14 output. Ignore MMC1 A14, ignore LSB of PRG bank, weird behavior of switchable PRG bank if PRG > 32KiB.

002, 003, 007: UxROM, CNROM, AxROM

Status: Draft

AxROM (mapper 7) is the only known licensed discrete logic mapper to unreliably come with bus conflict prevention circuitry. While no game documented in NesCartDB was released in one region on multiple board variants, several games did change boards when localized.

The following table is tentatively offered-
0: Normal (No advisory statement is made as to whether this game has bus conflicts) (uninvestigated AOROM)
1: Bus conflicts MUST NOT be enforced (ANROM)
2: Bus conflicts MUST be enforced (AMROM)

Although all Nintendo-manufactured games using normal CNROM (mapper 3), normal UxROM (mapper 2), and inverted UxROM (mapper 180) had bus conflicts, apparently several unlicensed games require their absence, as does the updated version of Donkey Kong with the pie factory level.[1] This same table should be used for them, too.

CNROM with security diodes (mapper 185) has a different set of submapper definitions.

004: MMC3

Status: Problem outline

No submapper of mapper 4 is needed to distinguish MMC3 from MMC6, as any board with MMC6-sized PRG RAM will behave like MMC6.

There are three known kinds of IRQ:

MMC3A

/IRQ is asserted on A12 rise, and loading the latch with 0 disables IRQ. Some chips labeled MMC3B also have this "old style" behavior.

MMC3C

/IRQ is asserted on A12 rise, and loading the latch with 0 produces an IRQ on every scanline. Some chips labeled MMC3B also have this "new style" behavior. Some later games rely on this behavior.

MC-ACC

/IRQ is asserted on A12 fall, typically four pixels later than MMC3A. It remains to be tested whether 0 acts like MMC3A or MMC3C. Found on second-source PCBs manufactured by Acclaim.

The TEROM and TFROM boards have two jumpers that can respectively disable IRQs and force hard-wired mirroring. It's not known if anything was ever released that used them.

Source: MMC3 submappers

005: MMC5

Status: Proposal

Vertical split mode:
0: SL
1: CL

If only one kind (battery or non-battery) of PRG-RAM present:
0: PRG-RAM is contiguous
2: PRG-RAM is not contiguous; is split in half across two chips

If two kinds of PRG-RAM present:
0: Chip 0 is battery-backed
2: Chip 1 is battery-backed

Volume:
0: R1 is 6.8kΩ (used in all games that use expansion audio)
4: R1 is 15kΩ (presumably the "proper" value of this resistor)

Bit3 probably does not need to be used. (It could be used for something, but probably shouldn't.)

019: Namco 129 and 163

Status: Problem outline

Mapper 19 designates the Namco 129 and 163, which supports expansion sound, IRQs, and ROM nametables.

Furthermore, different 163-using PCBs also used a different resistor to change the relative volume of the expansion audio relative to the internal 2A03 audio. It is unclear if this variation warrants a submapper.

KH allocated a submapper specifically for the N163-using game Mindseeker. It is not known what is different about this game.

Source: KH's submappers

021, 023, 025: VRC4

Konami's VRC4 mapper has five known variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper. These are spread across three mappers: two for 21, two for 25, and one for 23. There are theoretically 8*7 = 56 ways to wire these, but in all five extant possibilities, two adjacent address lines are used: A2 and A1, A0 and A1, A7 and A6, A2 and A3, and A3 and A2. All 14 combinations of two adjacent address lines easily fit in a submapper number:

3210
||||
|+++- Which address line corresponds is wired to the A1 in the VRC4a
+---- 0: Use next lower address line for VRC4a A2; 1: use next higher line

The values 0 (A0 and next lower) and 15 (A7 and next higher) are impossible.

The VRC4 article describes the ports by mapping them to the variant called "VRC4a" on that page, which uses A2 and A1, putting the four VRC IRQ ports (IRQ Latch low, IRQ Latch high, IRQ Control, and IRQ Acknowledge) at $F000, $F002, $F004, and $F006.

Nickname	A2	A1	Registers	iNES mapper	NES 2.0 submapper
VRC4a	A2	A1	$x000, $x002, $x004, $x006	21	9
VRC4b	A0	A1	$x000, $x002, $x001, $x003	25	1
VRC4c	A7	A6	$x000, $x040, $x080, $x0C0	21	14
VRC4d	A2	A3	$x000, $x008, $x004, $x00C	25	3
VRC4e	A3	A2	$x000, $x004, $x008, $x00C	23	10

023, 025: VRC2

Mappers 23 and 25 are used for both Konami's VRC2 and VRC4. It is tentatively suggested that submapper 15 (invalid per the VRC4 definitions) be used to mark VRC2-using games, to handle the bit at $6000 and lack of interrupts. Neither divides CHR bank select by two, unlike #22.

• 23.15 is VRC2 ($xxx0, $xxx1, $xxx2, $xxx3)
• 25.15 is VRC2 ($xxx0, $xxx2, $xxx1, $xxx3)

032: Irem G101

Status: Draft

Major League requires hardwired one-screen mirroring and entirely ignores writes to $9000.

0: Normal (H/V mapper-controlled mirroring)
1: CIRAM A10 is tied high (fixed one-screen mirroring) and PRG banking style is fixed as 8+8+16F

iNES Mapper 034

0: Normal (≤ 8KiB CHR implies BNROM, >8KiB CHR implies NINA-001)
1: Force NINA-001 behavior even with no CHR ROM

Source: KH's submappers

iNES Mapper 068 / Sunsoft 4

Status: Draft

Sunsoft 4 was used in Nantettatte!! Baseball, which invokes different PRG behavior:

The following table is tentatively offered-
0: Normal (max 256KiB PRG)
1: NTB-ROM (max 128KiB PRG, licensing IC present, external option ROM of up to 128KiB should be selectable by a second menu)

iNES Mapper 071

Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have hardwired horizontal or vertical mirroring.

0: Normal
1: Single-screen mirroring (Fire Hawk)

The Quattro multicarts have been moved to mapper 232.

Source: KH's submappers

iNES Mapper 078

One game uses this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. The other can switch between horizontal and vertical mirroring, using a multiplexer between PPU A10 and PPU A11 whose output is sent to CIRAM A10.

0: Not specified
1: Single-screen mirroring (nibble-swapped mapper 152)
2: Ignore mapper output and use fixed V/H/4 mirroring (effectively nibble-swapped mapper 70; not used in commercial games; deprecated)
3: Mapper-controlled H/V mirroring

Source: KH's submappers

iNES Mapper 185

Status: Draft

A few NROM-like games were released on CNROM boards where all four bits of the latch were solely used as an anti-piracy measure. While a documented heuristic exists for which values were used, we tentatively suggest that the submapper here indicate the value to be written to the latch for normal operation (submapper = (latch&0x30)/4+(latch&3))

3210  
||||
|||+- Bit 0 (bank number)
||+-- Bit 1 (bank number)
|+--- Bit 4 (diode config)
+---- Bit 5 (diode config)

In the case that any of the bits are "don't care", use 0.

210: Namco 175 and 340

Status: Problem outline

Mapper 210 doesn't distinguish between the 175's hardwired mirroring and 340's 1/H/V mirroring. Also, previous confusion and compatibility code used by Namco when they were developing games means that many 175- and 340- using games are incorrectly tagged as mapper 19.

Source: KH's submappers

iNES Mapper 232

Similar to #71 above, with a separate register controlling which 64 KiB outer bank of the PRG ROM is used. This is used for the Quattro multicarts.

0: Normal
1: Swap the bits of the outer bank number (for the Aladdin Deck Enhancer versions)