MMC3

The Nintendo MMC3 is a mapper ASIC used in Nintendo's TxROM Game Pak boards. Most common TxROM boards, along with HxROM boards (which use the Nintendo MMC6) are assigned to iNES Mapper 004; the TKSROM and TLSROM boards are assigned to iNES Mapper 118, and TQROM is assigned to iNES Mapper 119. This chip first appeared in the fall of 1988.

Overview

• PRG ROM size: Up to 512 KB
• PRG ROM bank size: 8 KB
• PRG RAM: Up to 8 KB
• CHR capacity: Up to 256 KB ROM or 8 KB RAM
• CHR bank size: 1 KB and 2 KB
• Nametable mirroring: Controlled by mapper
• Subject to bus conflicts: No

Banks

• CPU $6000-$7FFF: 8 KB PRG RAM bank
• CPU $8000-$9FFF (or $C000-$DFFF): 8 KB switchable PRG ROM bank
• CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
• CPU $C000-$DFFF (or $8000-$9FFF): 8 KB PRG ROM bank, fixed to the second-last bank
• CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
• PPU $0000-$07FF (or $1000-$17FF): 2 KB switchable CHR bank
• PPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bank
• PPU $1000-$13FF (or $0000-$03FF): 1 KB switchable CHR bank
• PPU $1400-$17FF (or $0400-$07FF): 1 KB switchable CHR bank
• PPU $1800-$1BFF (or $0800-$0BFF): 1 KB switchable CHR bank
• PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank

Registers

The MMC3 has 4 pairs of registers at $8000-$9FFF, $A000-$BFFF, $C000-$DFFF, and $E000-$FFFF - even addresses ($8000, $8002, etc.) select the low register and odd addresses ($8001, $8003, etc.) select the high register in each pair.

Bank select ($8000-$9FFE, even)

7  bit  0
---- ----
CPxx xRRR
||    |||
||    +++- Specify which bank register to update on next write to Bank Data register
||         0: Select 2 KB CHR bank at PPU $0000-$07FF (or $1000-$17FF);
||         1: Select 2 KB CHR bank at PPU $0800-$0FFF (or $1800-$1FFF);
||         2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF);
||         3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF);
||         4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF);
||         5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF);
||         6: Select 8 KB PRG bank at $8000-$9FFF (or $C000-$DFFF);
||         7: Select 8 KB PRG bank at $A000-$BFFF
|+-------- PRG ROM bank configuration (0: $8000-$9FFF swappable, $C000-$DFFF fixed to second-last bank;
|                                      1: $C000-$DFFF swappable, $8000-$9FFF fixed to second-last bank)
+--------- CHR ROM bank configuration (0: two 2 KB banks at $0000-$0FFF, four 1 KB banks at $1000-$1FFF;
                                       1: four 1 KB banks at $0000-$0FFF, two 2 KB banks at $1000-$1FFF)

Bank data ($8001-$9FFF, odd)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- New bank value, based on last value written to Bank select register (mentioned above)

The PRG banks are 8192 bytes in size, half the size of an iNES PRG bank. If your emulator or copier handles PRG data in 16384 byte chunks, you can think of the lower bit as selecting the first or second half of the bank:[1]

7  bit  0  When $8000 AND #$06 == #$06
---- ----
xxBB BBBH
  || ||||
  || |||+- 0: Select first half of this bank;
  || |||   1: Select second half of this bank
  ++-+++-- Select 16 KB PRG bank at $8000-$9FFF, $A000-$BFFF, or $C000-$DFFF

Mirroring ($A000-$BFFE, even)

7  bit  0
---- ----
xxxx xxxM
        |
        +- Mirroring (0: vertical; 1: horizontal)

PRG RAM protect ($A001-$BFFF, odd)

7  bit  0
---- ----
RWxx xxxx
||
|+-------- Write protection (0: allow writes; 1: deny writes)
+--------- Chip enable (0: disable chip; 1: enable chip)

IRQ latch ($C000-$DFFE, even)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- IRQ latch value

This register specifies the IRQ counter reload value. When the IRQ counter is zero (or a reload is requested through $C001), this value will be copied into the MMC3 IRQ counter at the end of the current scanline.

IRQ reload ($C001-$DFFF, odd)

7  bit  0
---- ----
xxxx xxxx

Writing any value to this register requests that the MMC3 IRQ counter be reloaded at the end of the current scanline.

IRQ disable ($E000-$FFFE, even)

7  bit  0
---- ----
xxxx xxxx

Writing any value to this register will disable MMC3 interrupts AND acknowledge any pending interrupts.

IRQ enable ($E001-$FFFF, odd)

7  bit  0
---- ----
xxxx xxxx

Writing any value to this register will enable MMC3 interrupts.

Hardware

The MMC3 most commonly exists in a 44-pin TQFP package. Three revisions are known to exist - MMC3A, MMC3B, and MMC3C. No major behavioral differences are known.

Acclaim's MC-ACC chip is their own variant of the MMC3, that they used for their own boards (for industrial money-saving purposes). It comes in a standard 600 mil 40-pin DIP package. It is not known if it has SRAM support, and no difference is known between this chip and the real MMC3.

The MMC3 scanline counter is based entirely on PPU A12, triggered on rising edges (after the line remains low for a sufficiently long period of time).

When the scanline counter is clocked, the value will first be checked. If it is zero, it will be reloaded from the IRQ latch ($C000); otherwise, it will decrement. If the old value in the counter is nonzero and new value is zero (whether from decrementing or reloading), an IRQ will be fired if IRQ generation is enabled (by writing to $E001).

Important points:

• The scanline counter cannot be stopped. It will continue to decrement and reload as long as PPU A12 on the PPU bus toggles.
• There is no direct access to the counter! The best you can do is update the reload value and immediately request a reload.
• Writing to $E000 will only prevent the MMC3 from generating IRQs - the counter will continue to run.
• Writing to $E001 will simply allow the MMC3 to generate IRQs - the counter remains unaffected.
• Writing to $C001 will cause the counter to be reloaded on the NEXT rising edge of PPU A12 instead of being decremented.
• Writing to $C000 does not immediately affect the value within the counter - this value is only used when the counter is reloaded, whether from reaching 0 or from writing to $C001.
• Whenever the counter changes from a non-zero value to $00, an IRQ will be generated (if enabled)
• The exact number of scanlines between IRQs is N+1, where N is the value written to $C000. 2 to 256 scanlines are supported.
• Writing $00 to $C000 will result in a single IRQ being generated on the next rising edge of PPU A12. No more IRQs will be generated until $C000 is changed to a non-zero value, upon which the counter will start counting from the new value, generating an IRQ once it reaches zero.
• The counter will not work properly unless you use different pattern tables for background and sprite data. The standard configuration is to use PPU $0000-$0FFF for background tiles and $1000-$1FFF for sprite tiles, whether 8x8 or 8x16.
• The counter is clocked on each rising edge of PPU A12, no matter what caused it, so it is possible to (intentionally or not) clock the counter by writing to $2006.

Some testing has shown that the various versions of the MMC3 behave differently when the IRQ counter is initialized to zero, though the exact relationship remains unknown.

It was found recently that all banks, in the case of CHR-RAM, are set to 0 on power up. More testing will be required to know if the same phenomenon happens for CHR-ROM.

Variants

The TKSROM and TLSROM boards connect the upper CHR bank select line directly to VRAM A10, allowing more flexible control over nametable mirroring.

The TQROM board uses both CHR ROM and CHR RAM simultaneously, using the 2nd-highest CHR bank select line to choose between them (on a per-bank basis).

DxROM carts have a custom mapper developed by Namco before the MMC3 existed. Tengen used it for some of their games under the name MIMIC-1. It exists both in a 400 mil 28-pin Shrink-DIP (found in licensed DxROM boards) and in a larger 600 mil 28-pin DIP (found in unlicensed Tengen cartridges). This chip does the basic PRGROM switching exactly like the MMC3, but it only implement the low 3 bits of $8000 and the low 5 bits of $8001. Compared to the MMC3, it lacks mirroring control, SRAM support and an IRQ counter. The TEROM and TFROM boards have been developed with backward compability with DxROM in mind, have solder pads to have hardwired H/V mirroring instead of MMC3 controlled mirroring, and allow to disable IRQs by hardware.