9112 pinout: Difference between revisions

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(added, fix it up)
 
(fixes, and same style as rest of pinouts on wiki)
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MMC3 clone, model 9112
MMC3 clone, model 9112


              .--\/--.
                  .--\/--.            
<-   CHR A10 |01  40| +5V
    (r) CHR A10 <- |01  40| -- VCC
->   PPU A12 |02  39| CHR A16   ->
    (f) PPU A12 -> |02  39| -> CHR A16 (r)
->   PPU A11 |03  38| CHR A11   ->
    (f) PPU A11 -> |03  38| -> CHR A11 (r)
->   PPU A10 |04  37|
    (f) PPU A10 -> |04  37| ??
<-   CHR A13 |05  36|
    (r) CHR A13 <- |05  36| ??
<-   CHR A14 |06  35| CPU D3   <-
    (r) CHR A14 <- |06  35| <- CPU D3 (fr)
<-   CHR A12 |07  34| CPU D2   <-
    (r) CHR A12 <- |07  34| <- CPU D2 (fr)
<- CIRAM A10 |08  33| CPU D4   <-
  (f) CIRAM A10 <- |08  33| <- CPU D4 (fr)
<-   CHR A15 |09  32| CPU D1   <-
    (r) CHR A15 <- |09  32| <- CPU D1 (fr)
<-   CHR A17 |10  31| CPU D5   <-
    (r) CHR A17 <- |10  31| <- CPU D5 (fr)
??  /ROMSEL |11  30| CPU D0   <-
    (f) /ROMSEL -> |11  30| <- CPU D0 (fr)
<-     /IRQ |12  29| CPU D6   <-
      (f) /IRQ <- |12  29| <- CPU D6 (fr)
->  CPU R/W |13  28| CPU A0   <-
        (f) R/W -> |13  28| <- CPU A0 (fr)
              |14  27| CPU D7   <-
    (r) PRG A15 <- |14  27| <- CPU D7 (fr)
->  PRG A13 |15  26| M2        <-
    (r) PRG A13 <- |15  26| <- M2 (f)
->   PRG A15 |16  25|
    (f) CPU A14 -> |16  25| ??
->  PRG A16 |17  24| PRG /CE
    (r) PRG A16 <- |17  24| -> PRG /CE (r)
->  PRG A14 |18  23|
    (r) PRG A14 <- |18  23| ??
->  PRG A18 |19  22| PRG A17   ->
    (r) PRG A18 <- |19  22| -> PRG A17 (r)
          GND |20  21| CPU A13   <-
            GND -- |20  21| <- CPU A13 (f)
              '------'
                  '------'            


== References ==
== References ==
*[http://forums.nesdev.org/viewtopic.php?p=156990#p156990 BBS]
*[http://forums.nesdev.org/viewtopic.php?p=156990#p156990 BBS]
[[Category:Pinouts]]
[[Category:Pinouts]]

Revision as of 23:07, 22 February 2016

MMC3 clone, model 9112

                  .--\/--.             
   (r) CHR A10 <- |01  40| -- VCC
   (f) PPU A12 -> |02  39| -> CHR A16 (r)
   (f) PPU A11 -> |03  38| -> CHR A11 (r)
   (f) PPU A10 -> |04  37| ??
   (r) CHR A13 <- |05  36| ??
   (r) CHR A14 <- |06  35| <- CPU D3 (fr)
   (r) CHR A12 <- |07  34| <- CPU D2 (fr)
 (f) CIRAM A10 <- |08  33| <- CPU D4 (fr)
   (r) CHR A15 <- |09  32| <- CPU D1 (fr)
   (r) CHR A17 <- |10  31| <- CPU D5 (fr)
   (f) /ROMSEL -> |11  30| <- CPU D0 (fr)
      (f) /IRQ <- |12  29| <- CPU D6 (fr)
       (f) R/W -> |13  28| <- CPU A0 (fr)
   (r) PRG A15 <- |14  27| <- CPU D7 (fr)
   (r) PRG A13 <- |15  26| <- M2 (f)
   (f) CPU A14 -> |16  25| ??
   (r) PRG A16 <- |17  24| -> PRG /CE (r)
   (r) PRG A14 <- |18  23| ??
   (r) PRG A18 <- |19  22| -> PRG A17 (r)
           GND -- |20  21| <- CPU A13 (f)
                  '------'             

References