User:Lidnariq/Discrete Logic Table: Difference between revisions
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m (footnote for m168 omitted an important detail) |
m (m180 only has 3 bits, but does have well-defined oversize) |
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| [[UxROM|UNROM]], [[iNES Mapper 094|94]] || || || || [[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹ || | | [[UxROM|UNROM]], [[iNES Mapper 094|94]], [[iNES Mapper 180|180]] || || || || [[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹ || | ||
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!4 | !4 | ||
| [[UxROM|UOROM | | [[UxROM|UOROM]] || || || || [[iNES Mapper 070|70]], [[iNES Mapper 092|92]] | ||
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!5 | !5 | ||
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!8 | !8 | ||
| oversize [[UxROM]] | | oversize [[UxROM]], oversize [[iNES Mapper 180|180]] | ||
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Revision as of 19:50, 3 February 2013
It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.
GxROM-like | 8kB CHR bank bits | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
32kB PRG bank bits | 0 | NROM | Vs. System | CNROM, 87, 101 | oversize CNROM | |||||
1 | AN1ROM¹ | MHROM | NINA-03/06 | |||||||
2 | ANROM¹, BNROM | GNROM, 38 | 86 | 11, 36, 140 | oversize 38 | |||||
3 | AOROM¹ | 113 | ||||||||
4 | oversize AxROM¹ | oversize GNROM | ||||||||
5 | ||||||||||
6 | ||||||||||
7 | ||||||||||
8 | oversize BNROM |
UxROM-like | 8kB CHR bank bits | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | ||
16kB PRG bank bits | 2 | 168† | ||||||
3 | UNROM, 94, 180 | 72, 78¹, 89¹, 93, 152¹ | ||||||
4 | UOROM | 70, 92 | ||||||
5 | ||||||||
6 | oversize 94 | |||||||
7 | ||||||||
8 | oversize UxROM, oversize 180 |
† 4F+4 CHR-RAM banking, not 8 CHR-ROM banking
¹ has mapper-controlled single-screen mirroring.