User:Lidnariq/Discrete Logic Table: Difference between revisions

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It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.
It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.


How on earth do I make these HTML tables look good in wiki markup?
{| class="datatable" style="text-align:center;"
|-
! colspan=2 rowspan=2| GxROM-like !! colspan="9" style="text-align:center;" rowspan="1"|8kB CHR bank bits
|-
!0 !! 1 !! 2 !! 3 !! 4 !! 5 !! 6 !! 7 !! 8
|-
! colspan="1" rowspan="9"|32kB PRG bank bits !! 0
| [[NROM]] || [[Vs. System]] || [[CNROM]], [[iNES Mapper 087|87]], [[iNES Mapper 101|101]] ||  ||  ||  ||  ||  || oversize [[CNROM]]
|-
!1
| [[AxROM|AN1ROM]]¹ ||  || [[GxROM|MHROM]] || [[NINA-003-006|NINA-03/06]] ||  ||  ||  ||
|-
!2
| [[AxROM|ANROM]]¹, [[BNROM]] ||  || [[GxROM|GNROM]], [[iNES Mapper 038|38]] || [[iNES Mapper 086|86]] || [[iNES Mapper 011|11]], [[iNES Mapper 036|36]], [[iNES Mapper 140|140]] ||  || oversize [[iNES Mapper 038|38]]
|-
!3
| [[AxROM|AOROM]]¹ ||  ||  ||  || [[iNES Mapper 113|113]] ||
|-
!4
| oversize [[AxROM]]¹ ||  ||  ||  || oversize [[GxROM|GNROM]]
|-
!5
|  ||  ||  ||
|-
!6
| 
|  ||
|-
!7
|  ||
|-
!8
| oversize [[BNROM]]
|}


<table border="1">
<tr><td colspan=2 rowspan=2>GxROM-like</td><td colspan="9" align="center" rowspan="1">8kB CHR bank bits</td></tr>
<tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td></tr>
<tr><td colspan="1" rowspan="9">32kB PRG bank bits</td><td>0</td><td>[[NROM]]</td><td>[[Vs. System]]</td><td>[[CNROM]], [[iNES Mapper 087|87]], [[iNES Mapper 101|101]]</td><td></td><td></td><td></td><td></td><td></td><td>oversize [[CNROM]]</td></tr>
<tr><td>1</td><td>[[AxROM|AN1ROM]]¹</td><td></td><td>[[GxROM|MHROM]]</td><td>[[NINA-003-006|NINA-03/06]]</td><td></td><td></td><td></td><td></td></tr>
<tr><td>2</td><td>[[AxROM|ANROM]]¹, [[BNROM]]</td><td></td><td>[[GxROM|GNROM]], [[iNES Mapper 038|38]]</td><td>[[iNES Mapper 086|86]]</td><td>[[iNES Mapper 011|11]], [[iNES Mapper 036|36]], [[iNES Mapper 140|140]]</td><td></td><td>oversize [[iNES Mapper 038|38]]</td></tr>
<tr><td>3</td><td>[[AxROM|AOROM]]¹</td><td></td><td></td><td></td><td>[[iNES Mapper 113|113]]</td><td></td></tr>
<tr><td>4</td><td>oversize [[AxROM]]¹</td><td></td><td></td><td></td><td>oversize [[GxROM|GNROM]]</td></tr>
<tr><td>5</td><td></td><td></td><td></td><td></td></tr>
<tr><td>6</td><td></td><td></td><td></td></tr>
<tr><td>7</td><td></td><td></td></tr>
<tr><td>8</td><td>oversize [[BNROM]]</td></tr>
</table>


<table border="1">
{| class="datatable"
<tr><td colspan=2 rowspan=2>UxROM-like</td><td colspan="7" align="center" rowspan="1">8kB CHR bank bits</td></tr>
|-
<tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td></tr>
! colspan=2 rowspan=2|UxROM-like !! colspan=7 style="text-align:center;"|8kB CHR bank bits
<tr><td colspan="1" rowspan="7">16kB PRG bank bits</td><td>2</td><td></td><td></td><td></td><td></td><td>[[iNES Mapper 168|168]]†</td><td></td><td></td></tr>
|-
<tr><td>3</td><td>[[UxROM|UNROM]], [[iNES Mapper 094|94]]</td><td></td><td></td><td></td><td>[[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹</td><td></td></tr>
!0 || 1 || 2 || 3 || 4 || 5 || 6
<tr><td>4</td><td>[[UxROM|UOROM]], [[iNES Mapper 180|180]]</td><td></td><td></td><td></td><td>[[iNES Mapper 070|70]], [[iNES Mapper 092|92]]</td></tr>
|-
<tr><td>5</td><td></td><td></td><td></td><td></td></tr>
! colspan=1 rowspan=7|16kB PRG bank bits || 2  
<tr><td>6</td><td>oversize [[iNES Mapper 094|94]]</td><td></td><td></td></tr>
|  ||  ||  ||  || [[iNES Mapper 168|168]]† ||  ||
<tr><td>7</td><td></td><td></td></tr>
|-
<tr><td>8</td><td>oversize [[UxROM]]</td></tr>
!3  
</table>
| [[UxROM|UNROM]], [[iNES Mapper 094|94]] ||  ||  ||  || [[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹ ||
|-
!4  
| [[UxROM|UOROM]], [[iNES Mapper 180|180]] ||  ||  ||  || [[iNES Mapper 070|70]], [[iNES Mapper 092|92]]
|-
!5  
|  ||  ||  ||
|-
!6  
| oversize [[iNES Mapper 094|94]] ||  ||
|-
!7  
|  ||
|-
!8  
| oversize [[UxROM]]
|}
 


† banks CHR-RAM, not CHR-ROM
† banks CHR-RAM, not CHR-ROM


¹ has mapper-controlled single-screen mirroring.
¹ has mapper-controlled single-screen mirroring.

Revision as of 19:58, 25 October 2012

It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.

GxROM-like 8kB CHR bank bits
0 1 2 3 4 5 6 7 8
32kB PRG bank bits 0 NROM Vs. System CNROM, 87, 101 oversize CNROM
1 AN1ROM¹ MHROM NINA-03/06
2 ANROM¹, BNROM GNROM, 38 86 11, 36, 140 oversize 38
3 AOROM¹ 113
4 oversize AxROM¹ oversize GNROM
5
6
7
8 oversize BNROM


UxROM-like 8kB CHR bank bits
0 1 2 3 4 5 6
16kB PRG bank bits 2 168†
3 UNROM, 94 72, 78¹, 89¹, 93, 152¹
4 UOROM, 180 70, 92
5
6 oversize 94
7
8 oversize UxROM


† banks CHR-RAM, not CHR-ROM

¹ has mapper-controlled single-screen mirroring.

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