User:Lidnariq/Discrete Logic Table: Difference between revisions

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m (miscounted number of bits for #92)
m (looks slightly better)
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<table border="1">
<table border="1">
<tr><td>GxROM-like</td><td></td><td colspan="9" align="center" rowspan="1">8kB CHR bank bits</td></tr>
<tr><td colspan=2 rowspan=2>GxROM-like</td><td colspan="9" align="center" rowspan="1">8kB CHR bank bits</td></tr>
<tr><td></td><td></td><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td></tr>
<tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td></tr>
<tr><td colspan="1" rowspan="9">32kB PRG bank bits</td><td>0</td><td>[[NROM]]</td><td></td><td>[[CNROM]], [[iNES Mapper 087|87]]</td><td></td><td></td><td></td><td></td><td></td><td>oversize [[CNROM]]</td></tr>
<tr><td colspan="1" rowspan="9">32kB PRG bank bits</td><td>0</td><td>[[NROM]]</td><td></td><td>[[CNROM]], [[iNES Mapper 087|87]]</td><td></td><td></td><td></td><td></td><td></td><td>oversize [[CNROM]]</td></tr>
<tr><td>1</td><td>[[AxROM|AN1ROM]]¹</td><td></td><td>[[GxROM|MHROM]]</td><td>[[iNES Mapper 079|79]]</td><td></td><td></td><td></td><td></td></tr>
<tr><td>1</td><td>[[AxROM|AN1ROM]]¹</td><td></td><td>[[GxROM|MHROM]]</td><td>[[iNES Mapper 079|79]]</td><td></td><td></td><td></td><td></td></tr>
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<table border="1">
<table border="1">
<tr><td>UxROM-like</td><td></td><td colspan="7" align="center" rowspan="1">8kB CHR bank bits</td></tr>
<tr><td colspan=2 rowspan=2>UxROM-like</td><td colspan="7" align="center" rowspan="1">8kB CHR bank bits</td></tr>
<tr><td></td><td></td><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td></tr>
<tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td></tr>
<tr><td colspan="1" rowspan="7">16kB PRG bank bits</td><td>2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr><td colspan="1" rowspan="7">16kB PRG bank bits</td><td>2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr><td>3</td><td>[[UxROM|UNROM]], [[iNES Mapper 094|94]]</td><td></td><td></td><td></td><td>[[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹</td><td></td></tr>
<tr><td>3</td><td>[[UxROM|UNROM]], [[iNES Mapper 094|94]]</td><td></td><td></td><td></td><td>[[iNES Mapper 072|72]], [[iNES Mapper 078|78]]¹, [[iNES Mapper 089|89]]¹, [[iNES Mapper 093|93]], [[iNES Mapper 152|152]]¹</td><td></td></tr>

Revision as of 07:09, 9 July 2012

It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style. Mappers with ¹ indicate those with mapper-controlled single-screen mirroring.

How on earth do I make these HTML tables look good in wiki markup?

GxROM-like8kB CHR bank bits
012345678
32kB PRG bank bits0NROMCNROM, 87oversize CNROM
1AN1ROM¹MHROM79
2ANROM¹, BNROMGNROM, 388611, 140oversize 38
3AOROM¹
4oversize AxROM¹oversize GNROM
5
6
7
8oversize BNROM
UxROM-like8kB CHR bank bits
0123456
16kB PRG bank bits2
3UNROM, 9472, 78¹, 89¹, 93, 152¹
4UOROM, 18070, 92
5
6
7
8oversize UxROM