Talk:Action 53 mapper: Difference between revisions
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== Pin count == | |||
Do few-enough-pin PALs/CPLDs still exist such that pointing out "there's no reason to connect D6 at all and D7 in mode selection could be changed to D5 and free up another input pin" is even remotely useful?—[[User:Lidnariq|Lidnariq]] 19:25, 13 October 2012 (MDT) | Do few-enough-pin PALs/CPLDs still exist such that pointing out "there's no reason to connect D6 at all and D7 in mode selection could be changed to D5 and free up another input pin" is even remotely useful?—[[User:Lidnariq|Lidnariq]] 19:25, 13 October 2012 (MDT) | ||
:It might free up pins in the current design, but I'm thinking ahead to how oversize expansions would work should the time come. And I don't see how you're getting 25 pins; it looks like 28 to me, especially with the equivalent of a [[PRG RAM circuit|7420 for PRG RAM decoding and bus conflict avoidance]] included. --[[User:Tepples|Tepples]] 20:30, 13 October 2012 (MDT) | |||
Revision as of 02:30, 14 October 2012
Pin count
Do few-enough-pin PALs/CPLDs still exist such that pointing out "there's no reason to connect D6 at all and D7 in mode selection could be changed to D5 and free up another input pin" is even remotely useful?—Lidnariq 19:25, 13 October 2012 (MDT)
- It might free up pins in the current design, but I'm thinking ahead to how oversize expansions would work should the time come. And I don't see how you're getting 25 pins; it looks like 28 to me, especially with the equivalent of a 7420 for PRG RAM decoding and bus conflict avoidance included. --Tepples 20:30, 13 October 2012 (MDT)
