CNROM

CNROM

Company	Nintendo, others
Boards	CNROM
PRG ROM capacity	32K
PRG ROM window	n/a
PRG RAM capacity	None
CHR capacity	32K
CHR window	8K
Nametable mirroring	Fixed H or V, controlled by solder pads
Bus conflicts	Yes
IRQ	No
Audio	No
iNES mappers	003, 185

NESCartDB

iNES 003

iNES 185

CNROM

NES-CNROM (and its HVC counterpart) is a particular Nintendo cartridge board which uses uses discrete logic to provide up to four 8 KB banks of CHR ROM. The most common usage of this board, as well as other third-party compatible boards, is assigned to iNES mapper 3. (See iNES Mapper 003 for the suggested emulator implementation.) A small collection of non-bankswitching CNROM boards that have an incompatible copy-protection issue are assigned to iNES Mapper 185.

Banks

• CPU $8000-$FFFF: 16 KB PRG ROM, fixed (if 16 KB PRG ROM used, then this is the same as $C000-$FFFF)
• CPU $C000-$FFFF: 16 KB PRG ROM, fixed
• PPU $0000-$1FFF: 8 KB switchable CHR ROM bank

For 16 KB PRG ROM testing, Joust (NES) makes a worthwhile test subject.

Registers

Bank select ($8000-$FFFF)

7  bit  0
---- ----
xxDD xxCC
  ||   ||
  ||   ++- Select 8 KB CHR ROM bank for PPU $0000-$1FFF
  ++------ Security diodes config

Hardware

The CNROM board contains a 74HC161 binary counter used as a quad D latch (4-bit register) to select the current CHR bank.

Early CNROM boards allow security diodes to be placed. If the latched bits 4 and 5 do not correspond to the configuration of the 2 diodes placed on the board while the PPU is rendering, the latched signal will conflict with some of the PPU's addresses bus and create bus conflicts. This system was probably created to make dumping cartridges harder, because the dumping device would have to write the correct value into the 74HC161 latch to dump the CHR ROM properly, or else bus conflicts will appear and possibly damage the dumping device. This anti-dump precaution wasn't very effective, and Nintendo quickly gave up on this. Only Japanese games released in 1986 are known to have these diodes present.

Some Japanese CNROM games combine the diode security with special CHR ROM where higher addresses are actually additional chip enable signals. This will cause the game's CHR ROM to be disabled at all if the wrong CHR bank is selected, making only one actual 8K CHR bank available (the games could in theory run in a NROM board without being affected). Those games typically turn the PPU off, switch in the wrong CHR bank (that return open bus) with wrong diode configuration, read a CHR byte in a specific place where the bus conflicts with the mapper will not appear even with the wrong diode config, then read the same byte with the correct bank and diode config latched, and enter in an infinite loop if the two reads matches. Those games have been assigned to iNES Mapper 185. Trying to dump them as regular NROM games will create bus conflicts with the dumping device, and even if this is bypassed the game will not run because the CHR ROM will be mirrored for all 8K bank select values.

Solder Pad Config

• Horizontal mirroring : 'H' disconnected, 'V' connected.
• Vertical mirroring : 'H' connected, 'V' disconnected.

• 16 KB PRG ROM : 'SL' connected, 'CL' disconnected.
• 32 KB PRG ROM : 'SL' disconnected, 'CL' connected.

• Bit 4 security implemented to '0' : D2 cathode set to '3' (CHR A12) and D2 anode set to '4' (latch).
• Bit 4 security implemented to '1' : D2 cathode set to '4' (latch) and D2 anode set to '3' (CHR A12).
• Bit 5 security implemented to '0' : D1 cathode set to '1' (CHR A10) and D1 anode set to '2' (latch).
• Bit 5 security implemented to '1' : D1 cathode set to '2' (latch) and D1 anode set to '1' (CHR A10).
• Security unimplemented : D1 and D2 not present.

Variants

CNROM operates identically to a GNROM with one PRG bank.

The upper 2 bank select bits on the 74HC161 were connected to security diodes. If they were connected to CHR ROM address lines instead, this board could have theoretically supported up to 128 KB of CHR ROM. In fact, iNES Mapper 003 encompasses both CNROM and similar boards that used more CHR ROM, such as those made by Bandai and Panesian.

The Japanese version of Dance Aerobics adds a sound playback IC to a CNROM-like board. It adds a register mapped from $6000-$7FFF that can play one of eight voice recordings. However, the specifics of the compression are not yet known, and there is no standardized way to bundle audio data with iNES images.

Hayauchi Super Igo is a CNROM-like board with a 2KB SRAM mapped at $6000, using a 74HC10 as the address decoder.

Theoretically the bank select register could be implemented with a 74HC377 octal D latch, allowing up to 2 megabytes of CHR ROM.

Notes

Many CNROM games such as Milon's Secret Castle store data tables in otherwise unused portions of CHR ROM and access them through PPUDATA ($2007) reads. If an emulator can show the title screen of the NROM game Super Mario Bros., but CNROM games don't work, the emulator's PPUDATA readback is likely failing to consider CHR ROM bankswitching.

See Also

• iNES Mapper 003 - The common emulator implementation used for this board, which includes some compatible additions.
• iNES Mapper 185 - Emulation for a subset of CNROM boards that implement a weak form of copy protection.
• Comprehensive NES Mapper Document by \Firebug\, information about mapper's initial state is inaccurate.