INES Mapper 116: Difference between revisions

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(VRC2 PRG registers are already 5 bits, not 4...)
(So with this in place, VRC2 mode isn't really that different from a VRC2. Rephrased to avoid "the emulator" verbiage. And explained from HW perspective what would provide "CHR ROM base offset")
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These boards appear to have been researched by Cah4e3. They're used for some chinese games and bootlegs. He has described them in fceu-mm sources as:
These boards appear to have been researched by CaH4e3. They're used for some chinese games and bootlegs. He has described them in fceu-mm sources as:


  * SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
  * SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
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These documents were verified by implementation into bizhawk based solely on the fceu-mm sources. FCEUX also possesses fceu-mm's sources for this mapper.
These documents were verified by implementation into bizhawk based solely on the fceu-mm sources. FCEUX also possesses fceu-mm's sources for this mapper.


This equipment is much simpler to operate than you might expect, considering that it is a combination of VRC2 + MMC3 + MMC1. There is a register:
This equipment is much simpler to operate than you might expect, considering that it is a combination of VRC2 + MMC3 + MMC1. The supervisor register controls which mapper's outputs are enabled:


   Range,Mask:  $4000-7FFF, $4100
   Range,Mask:  $4000-7FFF, $4100
     $4100:  [.... .CMM]
     $4100:  [.... .CMM]
       MM = Mapper mode
       MM = Mapper mode
           %00 = [[VRC2]]
           %00 = [[VRC2]]b
           %01 = [[MMC3]]
           %01 = [[MMC3]]
           %02, %03 = [[MMC1]]
           %02, %03 = [[MMC1]]
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The Mapper mode bits control which of the mapper circuits are connected to the NES. All of the PRG-based registers and IRQ signals are connected or disconnected accordingly. This means that in order to configure one of the mapper circuits, it must be connected.   
The Mapper mode bits control which of the mapper circuits are connected to the NES. All of the PRG-based registers and IRQ signals are connected or disconnected accordingly. This means that in order to configure one of the mapper circuits, it must be connected.   


The VRC2 acts somewhat differently from a stock VRC2. Fundamentally, the VRC2 registers are mapped as documented elsewhere as [[VRC2]]b, not suffering from any of the PCB address signal rewiring complexities as most of the VRC-based boards. The CHR regs must be initialized specially: the first four to $FF, at least. (SOMARI-W depends on this). There is no evidence for what the subsequent 4 CHR regs must be initialized to. Finally, it seems important that the emulator pay attention to all [[Mirroring#Memory Mirroring|mirror]]s of the registers in $8xxx, $9xxx, $Axxx: the game "Garou Densetsu Special" explicitly uses these. (Stock VRC-based boards also have these mirrors, but none of the games written by Konami used them.)
The VRC2 is wired as a [[VRC2]]b.
Though Konami games using VRC mappers write to only the canonical address of each port, games using this mapper such as ''Garou Densetsu Special'' tend to rely on being able to write to [[Mirroring#Memory Mirroring|mirror]]s of $8xxx, $9xxx, and $Axxx.
And ''SOMARI-W'' depends on the CHR bank registers being $FF at power on.


The MMC3 acts exactly as a stock TxROM. It has not been determined which MMC3 variant this MMC3 is acting as. Fceu-mm makes it seem as if the mmc3 CHR regs must be initialized at power-on in a certain pattern; it is unknown why this would be important.
The MMC3 acts exactly as a stock TxROM. It has not been determined which MMC3 variant this MMC3 is acting as. Fceu-mm makes it seem as if the mmc3 CHR regs must be initialized at power-on in a certain pattern; it is unknown why this would be important.
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The MMC1 acts exactly as a stock SxROM. Fceu-mm contained "hacky hacky" logic to do a reset of sorts on the MMC1 whenever the low bit of $41xx's address was set, claiming it was necessary for SOMARI-W.
The MMC1 acts exactly as a stock SxROM. Fceu-mm contained "hacky hacky" logic to do a reset of sorts on the MMC1 whenever the low bit of $41xx's address was set, claiming it was necessary for SOMARI-W.


The C bit of the m116's control reg simply provides a CHR ROM base offset for the VRC2 and MMC3 modes. After running the VRC2 or MMC3 logic, toss this extra signal onto the output CHR ROM address bus. One might speculate that this applies to MMC1 as well, but there is no evidence.
The C bit of the m116's control reg controls CHR ROM A18, which provides a CHR ROM base offset for the VRC2 and MMC3 modes. Whether and how this applies to the MMC1 mode has not been tested.


[[Category:iNES Mappers|116]][[Category:MMC3-like mappers|116]][[Category:Mappers using $4020-$5FFF|116]]
[[Category:iNES Mappers|116]][[Category:MMC3-like mappers|116]][[Category:Mappers using $4020-$5FFF|116]]

Revision as of 12:19, 24 October 2014

These boards appear to have been researched by CaH4e3. They're used for some chinese games and bootlegs. He has described them in fceu-mm sources as: 

* SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
* the same as 603-5052 board (TODO: add reading registers, merge)
* SL1632 2-in-1 protected board, similar to SL12 (TODO: find difference)

The following PCBs are listed as examples: 

* Garou Densetsu Special (G0904.PCB, Huang-1, GAL dip: W conf.)
* Kart Fighter (008, Huang-1, GAL dip: W conf.)
* Somari (008, C5052-13, GAL dip: P conf., GK2-P/GK2-V maskroms)
* Somari (008, Huang-1, GAL dip: W conf., GK1-P/GK1-V maskroms)
* AV Mei Shao Nv Zhan Shi ()
* Samurai Spirits (Full version) (Huang-1, GAL dip: unk conf. GS-2A/GS-4A maskroms)
* Contra Fighter (603-5052 board, C5052-3, GAL dip: unk conf. SC603-A/SCB603-B maskroms)

These documents were verified by implementation into bizhawk based solely on the fceu-mm sources. FCEUX also possesses fceu-mm's sources for this mapper.

This equipment is much simpler to operate than you might expect, considering that it is a combination of VRC2 + MMC3 + MMC1. The supervisor register controls which mapper's outputs are enabled: 

 Range,Mask:   $4000-7FFF, $4100
   $4100:  [.... .CMM]
     MM = Mapper mode
          %00 = VRC2b
          %01 = MMC3
          %02, %03 = MMC1
      C = 256K CHR ROM base (AV Girl Fighting uses this)

This control register supposedly occupies the WRAM address range, so there can be no WRAM. However, it only answers to $41xx.

The Mapper mode bits control which of the mapper circuits are connected to the NES. All of the PRG-based registers and IRQ signals are connected or disconnected accordingly. This means that in order to configure one of the mapper circuits, it must be connected.

The VRC2 is wired as a VRC2b. Though Konami games using VRC mappers write to only the canonical address of each port, games using this mapper such as Garou Densetsu Special tend to rely on being able to write to mirrors of $8xxx, $9xxx, and $Axxx. And SOMARI-W depends on the CHR bank registers being $FF at power on.

The MMC3 acts exactly as a stock TxROM. It has not been determined which MMC3 variant this MMC3 is acting as. Fceu-mm makes it seem as if the mmc3 CHR regs must be initialized at power-on in a certain pattern; it is unknown why this would be important.

The MMC1 acts exactly as a stock SxROM. Fceu-mm contained "hacky hacky" logic to do a reset of sorts on the MMC1 whenever the low bit of $41xx's address was set, claiming it was necessary for SOMARI-W.

The C bit of the m116's control reg controls CHR ROM A18, which provides a CHR ROM base offset for the VRC2 and MMC3 modes. Whether and how this applies to the MMC1 mode has not been tested.

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