Comparison of Nintendo mappers: Difference between revisions

Revision as of 07:34, 21 February 2012

This article compares the capabilities of several Nintendo mappers.

All of Nintendo's discrete logic mappers have bus conflicts except some revisions of 7.

iNES	Chips	Boards	Max PRG	PRG banks	Max CHR	CHR banks	Mirroring	PRG RAM?	IRQ
0	0	NROM	32		8		V/H hardwired	Rare	None
2	2	UNROM, UOROM	256	16 + 16F	8		V/H hardwired	No	None
3	1	CNROM	32		32	8	V/H hardwired	No	None
7	1-2	AxROM	256	32	8		1	No	None
13	1	CPROM (U)	32		16	4 + 4F	V/H hardwired	No	None
34	1	BNROM	256	32	8		V/H hardwired	No	None
180	2	UNROM	256	16F + 16	8		V/H hardwired	No	None

None of these ASIC mappers has bus conflicts.

iNES	Mapper	Boards	Max PRG ROM	PRG ROM banks	Max CHR	CHR banks	Mirroring	PRG RAM?	Assist
1	MMC1	SGROM, SNROM, SUROM	512	16 + 16F; 32	8	4 + 4	V/H/1 switchable	Optional	None
1	MMC1	SKROM, SLROM	256	16 + 16F; 32	128	4 + 4	V/H/1 switchable	Optional	None
4	MMC3	TxROM	512	8 + 8 + 16F	256	2 + 2 + 1 + 1 + 1 + 1	V/H switchable	Optional	Scanline IRQ
4	MMC3	TGROM, TNROM	512	8 + 8 + 16F	8	2 + 2 + 1 + 1 + 1 + 1	V/H switchable	Japan only	Scanline IRQ
118	MMC3	TKSROM, TLSROM	512	8 + 8 + 16F	128	2 + 2 + 1 + 1 + 1 + 1	Any switchable	Optional	Scanline IRQ
119	MMC3	TQROM	128	8 + 8 + 16F	64 + 8	2 + 2 + 1 + 1 + 1 + 1	V/H switchable	No	Scanline IRQ
5	MMC5	ExROM	512
9	MMC2	PNROM	128	8 + 24F	128	4/4 + 4/4	V/H switchable	No	Automatic CHR bank switching
10	MMC4	FJROM, FKROM (J)	256	16 + 16F	128	4/4 + 4/4	V/H switchable	Yes	Automatic CHR bank switching

@@ Line 2: / Line 2: @@
 == Discrete logic ==
-All of Nintendo's [[:Category:Discrete logic mappers|discrete logic mappers]] have bus conflicts except some revisions of 7.
+All of Nintendo's [[:Category:Discrete logic mappers|discrete logic mappers]] have [[bus conflict|bus conflicts]] except some revisions of 7.
 {| class="tabular"
 ! iNES || Chips || Boards || Max PRG || PRG banks || Max CHR || CHR banks || Mirroring || PRG RAM? || IRQ