User:Lidnariq/Discrete Logic Table: Difference between revisions
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<tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td></tr> | <tr><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td></tr> | ||
<tr><td colspan="1" rowspan="9">32kB PRG bank bits</td><td>0</td><td>[[NROM]]</td><td>[[Vs. System]]</td><td>[[CNROM]], [[iNES Mapper 087|87]], [[iNES Mapper 101|101]]</td><td></td><td></td><td></td><td></td><td></td><td>oversize [[CNROM]]</td></tr> | <tr><td colspan="1" rowspan="9">32kB PRG bank bits</td><td>0</td><td>[[NROM]]</td><td>[[Vs. System]]</td><td>[[CNROM]], [[iNES Mapper 087|87]], [[iNES Mapper 101|101]]</td><td></td><td></td><td></td><td></td><td></td><td>oversize [[CNROM]]</td></tr> | ||
<tr><td>1</td><td>[[AxROM|AN1ROM]]¹</td><td></td><td>[[GxROM|MHROM]]</td><td>[[ | <tr><td>1</td><td>[[AxROM|AN1ROM]]¹</td><td></td><td>[[GxROM|MHROM]]</td><td>[[NINA-003-006|NINA-03/06]]</td><td></td><td></td><td></td><td></td></tr> | ||
<tr><td>2</td><td>[[AxROM|ANROM]]¹, [[BNROM]]</td><td></td><td>[[GxROM|GNROM]], [[iNES Mapper 038|38]]</td><td>[[iNES Mapper 086|86]]</td><td>[[iNES Mapper 011|11]], [[iNES Mapper 036|36]], [[iNES Mapper 140|140]]</td><td></td><td>oversize [[iNES Mapper 038|38]]</td></tr> | <tr><td>2</td><td>[[AxROM|ANROM]]¹, [[BNROM]]</td><td></td><td>[[GxROM|GNROM]], [[iNES Mapper 038|38]]</td><td>[[iNES Mapper 086|86]]</td><td>[[iNES Mapper 011|11]], [[iNES Mapper 036|36]], [[iNES Mapper 140|140]]</td><td></td><td>oversize [[iNES Mapper 038|38]]</td></tr> | ||
<tr><td>3</td><td>[[AxROM|AOROM]]¹</td><td></td><td></td><td></td><td></td><td></td></tr> | <tr><td>3</td><td>[[AxROM|AOROM]]¹</td><td></td><td></td><td></td><td>[[iNES Mapper 113|113]]</td><td></td></tr> | ||
<tr><td>4</td><td>oversize [[AxROM]]¹</td><td></td><td></td><td></td><td>oversize [[GxROM|GNROM]]</td></tr> | <tr><td>4</td><td>oversize [[AxROM]]¹</td><td></td><td></td><td></td><td>oversize [[GxROM|GNROM]]</td></tr> | ||
<tr><td>5</td><td></td><td></td><td></td><td></td></tr> | <tr><td>5</td><td></td><td></td><td></td><td></td></tr> | ||
Revision as of 22:43, 21 October 2012
It appears that all discrete logic mappers either switch 32kB at a time with no fixed bank ("GxROM-like"), or have a 16kB fixed bank and can switch the other ("UxROM-like"). The tables below illustrate the tradeoffs between CHR, PRG, and banking style.
How on earth do I make these HTML tables look good in wiki markup?
| GxROM-like | 8kB CHR bank bits | |||||||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
| 32kB PRG bank bits | 0 | NROM | Vs. System | CNROM, 87, 101 | oversize CNROM | |||||
| 1 | AN1ROM¹ | MHROM | NINA-03/06 | |||||||
| 2 | ANROM¹, BNROM | GNROM, 38 | 86 | 11, 36, 140 | oversize 38 | |||||
| 3 | AOROM¹ | 113 | ||||||||
| 4 | oversize AxROM¹ | oversize GNROM | ||||||||
| 5 | ||||||||||
| 6 | ||||||||||
| 7 | ||||||||||
| 8 | oversize BNROM | |||||||||
| UxROM-like | 8kB CHR bank bits | |||||||
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | ||
| 16kB PRG bank bits | 2 | 168† | ||||||
| 3 | UNROM, 94 | 72, 78¹, 89¹, 93, 152¹ | ||||||
| 4 | UOROM, 180 | 70, 92 | ||||||
| 5 | ||||||||
| 6 | oversize 94 | |||||||
| 7 | ||||||||
| 8 | oversize UxROM | |||||||
† banks CHR-RAM, not CHR-ROM
¹ has mapper-controlled single-screen mirroring.
