Talk:PPU pinout: Difference between revisions
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Through analysis of Visual2C02 and cross-referencing of the [http://nesdev.org/Ntd_8bit.jpg Family Computer schematic], I've decided to rename pin 22 from "/SYNC" to "/RST" because that's clearly what it does (and I also renamed /VBL to /INT). However, there is still the matter of this comment: "(In a dual-PPU arrangement, the master /INT is also connected to the slave's /RST input)". This ''cannot'' be the case, because it would result in the chips becoming '''desynchronized''' - /INT goes high at the beginning of scanline 261 (pre-render), but /RST places the chip at the beginning of scanline 0 '''and''' forces rendering to be disabled for a complete frame. --[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 09:33, 31 March 2013 (MDT) | Through analysis of Visual2C02 and cross-referencing of the [http://nesdev.org/Ntd_8bit.jpg Family Computer schematic], I've decided to rename pin 22 from "/SYNC" to "/RST" because that's clearly what it does (and I also renamed /VBL to /INT). However, there is still the matter of this comment: "(In a dual-PPU arrangement, the master /INT is also connected to the slave's /RST input)". This ''cannot'' be the case, because it would result in the chips becoming '''desynchronized''' - /INT goes high at the beginning of scanline 261 (pre-render), but /RST places the chip at the beginning of scanline 0 '''and''' forces rendering to be disabled for a complete frame. --[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 09:33, 31 March 2013 (MDT) | ||
:I imagine that the two chips' /RST inputs would be tied together. There'd also have to be glue logic to keep some semblance of synchronization between writes to $2001 on both PPUs so that neither PPU is put in a state where one skips the dot between pre-render and the first line of picture and the other does not. --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 12:32, 31 March 2013 (MDT) | :I imagine that the two chips' /RST inputs would be tied together. There'd also have to be glue logic to keep some semblance of synchronization between writes to $2001 on both PPUs so that neither PPU is put in a state where one skips the dot between pre-render and the first line of picture and the other does not. --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 12:32, 31 March 2013 (MDT) | ||
: Yeah, the more dwe refined the functions of the pins, the less I trusted that comment.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 13:23, 31 March 2013 (MDT) | |||
Revision as of 19:23, 31 March 2013
EXT port description
Can the function of the EXT pins be described more precisely? I do not understand very well, there are four EXT pins, and the colors are six bits (selecting the palette entry is only two bits), so how can it decide the color from this? --Zzo38 (talk) 00:27, 21 January 2013 (MST)
- I am having a doozy of a time figuring out how to rephrase it on the main page in an intelligible manner, so I'll just start from scratch: Assume the NES's palette has no gaps and thus is a {32 entry} × {6 bit} array. log₂(32)=5, so indexing this array requires 5 bits. The EXT port takes as input or output the bottom 4 bits of this 5 bit index. If the EXT port is used as an input, it replaces the "transparent" color in index 0 with any of colors 0-15, i.e. it's an extra layer of background and background-colored sprites underneath. —Lidnariq (talk) 01:59, 21 January 2013 (MST)
SYNC -> RST
Through analysis of Visual2C02 and cross-referencing of the Family Computer schematic, I've decided to rename pin 22 from "/SYNC" to "/RST" because that's clearly what it does (and I also renamed /VBL to /INT). However, there is still the matter of this comment: "(In a dual-PPU arrangement, the master /INT is also connected to the slave's /RST input)". This cannot be the case, because it would result in the chips becoming desynchronized - /INT goes high at the beginning of scanline 261 (pre-render), but /RST places the chip at the beginning of scanline 0 and forces rendering to be disabled for a complete frame. --Quietust (talk) 09:33, 31 March 2013 (MDT)
- I imagine that the two chips' /RST inputs would be tied together. There'd also have to be glue logic to keep some semblance of synchronization between writes to $2001 on both PPUs so that neither PPU is put in a state where one skips the dot between pre-render and the first line of picture and the other does not. --Tepples (talk) 12:32, 31 March 2013 (MDT)
- Yeah, the more dwe refined the functions of the pins, the less I trusted that comment.—Lidnariq (talk) 13:23, 31 March 2013 (MDT)
