INES Mapper 243: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(There's a term on the mirroring page for the odd mode that %10 produces)
(→‎Register Data ($4101, read/write): call out that all registers can be fully read and written. fix typo in R4)
 
(15 intermediate revisions by 3 users not shown)
Line 1: Line 1:
[[Category:iNES Mappers|243]][[Category:Mappers using $4020-$5FFF|243]]
{{DEFAULTSORT:243}}[[Category:iNES Mappers]][[Category:Mappers using $4020-$5FFF]]
  Based on Disch's original notes: 
'''iNES Mapper 243''' denotes the Sachen '''SA-020A''' circuit board. Using an eight-register ASIC with a fake "[[Sachen 74LS374N pinout|74LS374N]]" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, ''美女拳 - Honey Peach'' (SA-006).
  ========================
 
  = Mapper 243          =
=Banks=
  ========================
* CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
 
* PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
 
* Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen
  Example Games:
 
  --------------------------
=Registers=
  Honey
==Register Index ($4100, write)==
  Poker III 5-in-1
Mask: $C101
 
 
D~7654 3210
  Registers:
  ---------
  ---------------------------
  .... .RRR
 
        +++- Select register number (Rx)
  Range,Mask:  $4020-4FFF, $4101
 
 
==Register Data ($4101, read/write)==
    $4100:  [.... .AAA]  Address for use with $4101
Mask: $C101
 
    $4101:   Data port
D~7654 3210
      R:2 -> [.... ...H] High bit of CHR reg
  ---------
      R:4 -> [.... ...L] Low bit of CHR reg
  .... .RRR
      R:5 -> [.... .PPP]  PRG reg  (32k @ $8000)
        +++- Register data
      R:6 -> [.... ..DD] Middle bits of CHR reg
      R:7 -> [.... .MM.] Mirroring
D~7654 3210
          %00 = Horz
  ---------
          %01 = Vert
  .... ...A  R2: CHR A13
          %10 = L-shaped; see below
  .... ...B R4: CHR A14
          %11 = 1ScB
  .... ..PP R5: PRG A16..A15
 
  .... ..DC R6: CHR A16..A15
 
  ... .MM.  R7: Nametable mirroring
  Mirroring:
              0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L)
  ---------------------------
              1: Horizontal
 
              2: Vertical
  Mirroring mode %10 is not quite 1ScB:
              3: Single-screen, page 1
 
Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to.
    [ NTA  ][ NTB  ]
 
    [  NTB  ][  NTB  ]
=Errata=
 
The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.
 
 
  CHR Setup:
=See also=
  ---------------------------
* [https://www.flickr.com/photos/153392699@N08/sets/72157682682439086 Box, Cart, and PCB picture of ''Honey Peach'']
 
  8k CHR page @ $0000 is selected by the given 4 bit CHR page number ('HDDL')

Latest revision as of 19:21, 14 December 2019

iNES Mapper 243 denotes the Sachen SA-020A circuit board. Using an eight-register ASIC with a fake "74LS374N" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, 美女拳 - Honey Peach (SA-006).

Banks

  • CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
  • PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
  • Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen

Registers

Register Index ($4100, write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Select register number (Rx)

Register Data ($4101, read/write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Register data

D~7654 3210
  ---------
  .... ...A  R2: CHR A13
  .... ...B  R4: CHR A14
  .... ..PP  R5: PRG A16..A15
  .... ..DC  R6: CHR A16..A15
  ...  .MM.  R7: Nametable mirroring
              0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L)
              1: Horizontal
              2: Vertical
              3: Single-screen, page 1

Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to.

Errata

The SA-150 PCB, denoted by INES Mapper 150, connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.

See also

Retrieved from "https://www.nesdev.org/w/index.php?title=INES_Mapper_243&oldid=5861"