Mask ROM pinout: Difference between revisions

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== 8kB / 16kB / 32kB / 64kBytes (28pin) ROMs ==
== 8kB / 16kB / 32kB / 64kBytes (28pin) ROMs ==


Nintendo used by default JEDEC standard compatible pinout for all their mask ROMs of 64 kByes and below. Names [in brackets] applies when the corresponding address pin is unused. On boards where an adress pin is never used (for example, A15 is never used on [[NROM]] boards as the ROM can't be greater than 32k), what is in brackets connects to the unused pin.
Nintendo used by default JEDEC standard compatible pinouts for all their mask ROMs of 64 kBytes and below (but some particular boards might be exceptions !).
Names [in brackets] applies when the corresponding address pin is unused. On boards where an adress pin is never used (for example, A15 is never used on [[NROM]] boards as the ROM can't be greater than 32k), what is in brackets connects to the unused pin.


For some unknown reasons, unused address lines on smaller ROMs '''had to be''' put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though.
For some unknown reasons, unused address lines on smaller ROMs '''had to be''' put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though.
As Nintendo liked to use Mask ROMs from various manufacturers, apparently unused pins could be either not connected or additional active high CE enable lines. This would ensure that if Nintendo would order mask ROMs with additional enable lines that aren't used, they could place them on the board without having the fear of having them disabled accidentally.


This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind.
This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind. Probably as the game will work if the ROM is "accidentally" disabled before the first write to CHR bankswitching registers.


<pre style="display:inline-block">
   27C64/128/256/512 EPROM pinout
   27C64/128/256/512 EPROM pinout
   
   
Line 26: Line 27:
         GND - |14  15| - D3
         GND - |14  15| - D3
               -------
               -------
</pre>
<pre style="display:inline-block">
              PRG ROM pinout
                  ---_---
[+5V] PRG A15 - |01  28| - +5V
      PRG A12 - |02  27| - PRG A14 [+5V]
      PRG A7  - |03  26| - PRG A13 [N/C]
      PRG A6  - |04  25| - PRG A8
      PRG A5  - |05  24| - PRG A9
      PRG A4  - |06  23| - PRG A11
      PRG A3  - |07  22| - PRG /CE
      PRG A2  - |08  21| - PRG A10
      PRG A1  - |09  20| - GND
      PRG A0  - |10  19| - PRG D7
      PRG D0  - |11  18| - PRG D6
      PRG D1  - |12  17| - PRG D5
      PRG D2  - |13  16| - PRG D4
      GND    - |14  15| - PRG D3
                  -------
</pre>
<pre style="display:inline-block">
              CHR ROM pinout
                  ---_---
      +5V    - |01  28| - +5V
      CHR A12 - |02  27| - PRG A14
      CHR A7  - |03  26| - PRG A13
      CHR A6  - |04  25| - CHR A8
      CHR A5  - |05  24| - CHR A9
      CHR A4  - |06  23| - CHR A11
      CHR A3  - |07  22| - /OE (CHR /RD)
      CHR A2  - |08  21| - CHR A10
      CHR A1  - |09  20| - /CE (CHR A13)
      CHR A0  - |10  19| - CHR D7
      CHR D0  - |11  18| - CHR D6
      CHR D1  - |12  17| - CHR D5
      CHR D2  - |13  16| - CHR D4
      GND    - |14  15| - CHR D3
                  -------
</pre>


== 128/256/512 KBytes (28/32pin) ROMs ==
== 128/256/512 KBytes (28/32pin) ROMs ==


Nintendo used the JEDEC pinout for (extremely rare) prototype boards intended to take a 27C010/020/040 EPROM.
Nintendo used the standard pinout for (extremely rare) prototype boards intended to take a 27C010/020/040 EPROM.
But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not JEDEC compatible.
But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not compatible.
This pinout, with reshuffled enable lines and higher address lines (highlighted in **), allows a 32-pin hole to take a 28-pin 128 KB PRG ROM in pin 3 to pin 30.
This pinout, with reshuffled enable lines and higher address lines, allows a 32-pin hole to take a 28-pin 128 KiB PRG ROM in pin 3 to pin 30.


Other companies producing Famicom boards with ROMs of those sizes, notably Konami, used either epoxy blobs or JEDEC pinout.
For games using 256 KiB and larger ROMs, other companies producing Famicom or NES boards used either epoxy blobs or standard EPROM pinout. But games with 128 KiB of PRG were more often in a 28-pin package than not.


On boards where PRG A18 is never used, pin 2 is connected with pin 22.
On Nintendo's boards where PRG A18 is never used, pin 2 is connected with pin 22.
 
Nintendo's MMC5 boards use the same pinout for both PRG and CHR ROMs, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin.


<pre style="display:inline-block">
<pre style="display:inline-block">
  27C010/020/040/80 EPROM pinout
        CHR ROM, PRG ROM, and 27C010/020/040/080 EPROM pinouts compared
        (JEDEC standard)
            ---_---
[VPP] A19 - |01  32| - +5V
      A16 - |02  31| - A18 [PGM]
      A15 - |03  30| - A17 [NC]
      A12 - |04  29| - A14
      A7  - |05  28| - A13
      A6  - |06  27| - A8
      A5  - |07  26| - A9
      A4  - |08  25| - A11
      A3  - |09  24| - /OE
      A2  - |10  23| - A10
      A1  - |11  22| - /CE
      A0  - |12  21| - D7
      D0  - |13  20| - D6
      D1  - |14  19| - D5
      D2  - |15  18| - D4
      GND - |16  17| - D3
            -------
</pre>
<pre style="display:inline-block">
          Nintendo PRG ROM pinout
   
   
                  ---_---
  MMC5    CHR       PRG     EPROM                  EPROM       PRG  CHR   MMC5
      PRG A17 - |01  32| - +5V
                                        ---_---
**[/CE]PRG A18 - |02  31| - +5V **
  A17    A17 [+5V] A17     [VPP] A19 - |01  32| - +5V
      PRG A15 - |03  30| - +5V **
A18    /OE        A18 [/CE]      A16 - |02  31| - A18 [PGM]    +5V    /CE    /CE
      PRG A12 - |04  29| - PRG A14
                                  A15 - |03  30| - A17 [NC]    +5V   +5V    A19
      PRG A7 - |05  28| - PRG A13
                                  A12 - |04  29| - A14
       PRG A6  - |06  27| - PRG A8
                                  A7  - |05  28| - A13
       PRG A5  - |07   26| - PRG A9
                                  A6  - |06  27| - A8
      PRG A4  - |08   25| - PRG A11
                                  A5  - |07  26| - A9
      PRG A3  - |09  24| - PRG A16 **
                                  A4  - |08  25| - A11
      PRG A2  - |10  23| - PRG A10
                                  A3  - |09  24| - /OE          A16    A16    A16
      PRG A1  - |11  22| - PRG /CE
                                  A2  - |10  23| - A10
      PRG A0 - |12  21| - PRG D7
                                  A1  - |11  22| - /CE                GND
      PRG D0  - |13  20| - PRG D6
                                  A0  - |12  21| - D7
      PRG D1  - |14  19| - PRG D5
                                  D0  - |13  20| - D6
      PRG D2  - |15  18| - PRG D4
                                  D1  - |14  19| - D5
      GND    - |16  17| - PRG D3
                                  D2  - |15  18| - D4
                  -------
                                  GND - |16  17| - D3
</pre>
                                        -------
<pre style="display:inline-block">
 
          Nintendo CHR ROM pinout
PRG and CHR pins are listed only if they differ from EPROM.
 
                  ---_---
**[+5V]CHR A17 - |01  32| - +5V
**(CHR /RD)/OE - |02  31| - /CE (CHR A13) **
      CHR A15 - |03  30| - +5V **
      CHR A12 - |04  29| - CHR A14
      CHR A7  - |05  28| - CHR A13
      CHR A6  - |06  27| - CHR A8  
      CHR A5  - |07  26| - CHR A9
      CHR A4  - |08  25| - CHR A11
      CHR A3  - |09  24| - CHR A16 **
      CHR A2  - |10  23| - CHR A10
      CHR A1  - |11  22| - GND (/OE ?)
      CHR A0  - |12  21| - CHR D7
      CHR D0  - |13  20| - CHR D6
      CHR D1  - |14  19| - CHR D5
      CHR D2  - |15  18| - CHR D4
      GND     - |16  17| - CHR D3
                  -------
</pre>
</pre>


Line 149: Line 71:
Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold).
Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold).


=== Nintendo MMC5 PRG/CHR ROM pinouts - 128/256/512/1024 kBytes (32pin) ===
=== Nintendo RROM CHR ROM pinout - 8 KBytes (28pin) ===


Variant of Nintendo's pinouts just above for MMC5 boards which supports up to 1MB of data. Both PRG and CHR ROMs are the same pinout, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin.
This particular board is functionally identical to NROM but with a strange CHR pinout :


{|
  [https://nescartdb.com/nescartdb.com/profile/view/2314 RROM] Non-standard 64-kbit CHR pinout
|
              ---_---
      Nintendo MMC5 PRG ROM pinout
      '''A7''' - |01  28| - +5V
      '''A6''' - |02  27| - '''A8'''
          ----_----  
      '''A5''' - |03  26| - '''A9'''
  PRG A17 - |01  32| - +5V
      '''A4''' - |04  25| - '''A12'''
  PRG A18 - |02  31| - PRG /CE
      '''A3'''  - |05  24| - '''/CE'''
  PRG A15 - |03  30| - '''PRG A19 '''
      '''+5V''' - |06  23| - '''NC'''
  PRG A12 - |04  29| - PRG A14
      '''+5V''' - |07  22| - /OE
  PRG A7 - |05  28| - PRG A13
      A2  - |08  21| - A10
  PRG A6 - |06  27| - PRG A8
      A1 - |09   20| - '''A11'''
  PRG A5 - |07  26| - PRG A9
      A0 - |10   19| - D7
  PRG A4 - |08  25| - PRG A11
      D0 - |11   18| - D6
  PRG A3 - |09  24| - PRG A16
      D1 - |12   17| - D5
  PRG A2 - |10  23| - PRG A10  
      D2 - |13   16| - D4
  PRG A1 - |11   22| - '''/OE (GND)'''
      GND - |14   15| - D3
  PRG A0 - |12   21| - PRG D7
              -------
  PRG D0 - |13   20| - PRG D6  
 
  PRG D1 - |14   19| - PRG D5  
=== Nintendo SROM CHR ROM pinout - 8 KBytes (24pin) ===
  PRG D2 - |15   18| - PRG D4  
 
    GND - |16   17| - PRG D3  
This particular board is functionally identical to NROM but the CHR uses a 24-pin 8KB ROM with pinout very similar to the 27C32:
            -------
 
|
  SROM 23C62/64 JEDEC-Standard 64-kbit CHR pinout
      Nintendo MMC5 CHR ROM pinout
            ---_---
      A7 - |01   24| - Vcc
          ----_----  
      A6 - |02   23| - A8
  CHR A17 - |01  32| - +5V
      A5 - |03   22| - A9
'''CHR A18''' - |02  31| - '''/CE (CHR A13)'''
      A4 - |04   21| - '''A12'''
CHR A15 - |03  30| - '''CHR A19'''
      A3 - |05   20| - /OE
CHR A12 - |04  29| - CHR A14
      A2 - |06   19| - A10
  CHR A7 - |05   28| - CHR A13
      A1 - |07   18| - '''A11'''
  CHR A6 - |06   27| - CHR A8
      A0 - |08   17| - D7
  CHR A5 - |07   26| - CHR A9
      D0 - |09   16| - D6
  CHR A4 - |08   25| - CHR A11
      D1 - |10   15| - D5
  CHR A3 - |09   24| - CHR A16
      D2 - |11   14| - D4
  CHR A2 - |10   23| - CHR A10
      Gnd - |12   13| - D3
  CHR A1 - |11   22| - '''/OE (CHR /RD)'''
            -------
  CHR A0 - |12   21| - CHR D7
 
  CHR D0 - |13   20| - CHR D6
With only one output enable, the board synthesizes the signal (/OE = PPU A13 + PPU /RD) using two transistors and a resistor.
  CHR D1 - |14   19| - CHR D5
 
  CHR D2 - |15   18| - CHR D4
=== Nintendo STROM ===
    GND - |16   17| - CHR D3
This board uses three 23C62, 8 KBytes, 24 pin MASK ROMs (two as PRG-ROM and one as CHR-ROM) and a few discrete elements for an address decoder [https://forums.nesdev.org/viewtopic.php?f=9&t=3447&p=274110#p25434]
            -------
|}


=== Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin) ===
=== Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin) ===
Line 202: Line 122:
Very slight variant of the standard PRG-ROM pinout above, where an additional active high enable line is used to prevent bus conflicts.
Very slight variant of the standard PRG-ROM pinout above, where an additional active high enable line is used to prevent bus conflicts.


                  ---_---
              ---_---
      PRG A17 - |01  32| - +5V
        A17 - |01  32| - +5V
      PRG /CE - |02  31| - '''CE (R/W)'''
        /CE - |02  31| - '''CE (R/W)'''
      PRG A15 - |03  30| - +5V
        A15 - |03  30| - +5V
      PRG A12 - |04  29| - PRG A14
        A12 - |04  29| - A14
      PRG A7  - |05  28| - PRG A13
        A7  - |05  28| - A13
      PRG A6  - |06  27| - PRG A8  
        A6  - |06  27| - A8  
      PRG A5  - |07  26| - PRG A9
        A5  - |07  26| - A9
      PRG A4  - |08  25| - PRG A11
        A4  - |08  25| - A11
      PRG A3  - |09  24| - PRG A16
        A3  - |09  24| - A16
      PRG A2  - |10  23| - PRG A10
        A2  - |10  23| - A10
      PRG A1  - |11  22| - PRG /CE
        A1  - |11  22| - /CE
      PRG A0  - |12  21| - PRG D7
        A0  - |12  21| - D7
      PRG D0  - |13  20| - PRG D6
        D0  - |13  20| - D6
      PRG D1  - |14  19| - PRG D5
        D1  - |14  19| - D5
      PRG D2  - |15  18| - PRG D4
        D2  - |15  18| - D4
       GND     - |16  17| - PRG D3
       GND - |16  17| - D3
                  -------
              -------
 
Japanese ''After Burner'' connects two such 128 kB mask roms in parallel (pin 2 = PPU /RD, pin 22 = SS4-CHR-/CE, pin31 = SS4-CHR-A17), which implies that one of them needs to have pin 31 active low and the other active high. [https://nescartdb.com/profile/view/3806/after-burner]


== Signal descriptions ==
== Signal descriptions ==
;A0-A12 : address
;A0-A12 : address
;D0-D7 : data
;D0-D7 : data
;/CE, /OE : The ROM will output data at adress A on pins D only if all it's CE and OE pins are active (CE active high, /CE active low).
;/CE, /OE : The ROM will output data at address A on pins D only if all its CE (chip enable) and OE (output enable) pins are active (CE active high, /CE active low). /CE is sometimes called /CS (chip select). A memory responds faster to /OE than to /CE but draws less current while /CE is not asserted.
;PGM, VPP : Used only during EPROM programing / erasing process.
;PGM, VPP : Used only during EPROM programing / erasing process.


See [[Cartridge connector#Signal Descriptions|here]] for other signals descriptions.
See [[Cartridge connector#Signal Descriptions|Cartridge connector]] for other signals descriptions.
 
== Converting a donor board ==
 
To convert a cartridge board to accept EPROM:
# Compare the pinout of your EPROM to the mask ROM pinout expected by the board.
# Lift any pins whose signals differ.
# Solder short wires to the corresponding holes.
# Solder down the memory or socket with the pins that do not differ.
# Solder each lifted pin to the hole with the same signal.
 
== See also ==
* [http://nesdev.org/NES%20EPROM%20Conversions.txt NES EPROM Conversions] by Drk. Instructions on how to modify certain boards to use EPROMs.
* [http://nesdev.org/NES%20ROM%20Pinouts.txt NES ROM pinouts] by Drk. Covers all PRG, CHR, and RAM chips used in NES cartridges.
* [http://nesdev.org/EPROM%20Pinouts.txt EPROM pinouts] by Drk.
* [http://callanbrown.com/index.php/advanced-mmc3-nes-reproduction Advanced MMC3 NES Reproduction Tutorial] by Callan Brown
* [http://forums.nesdev.org/viewtopic.php?p=171375#p171375 SNROM to SUROM] by Ice Man
 
[[Category:Pinouts]]

Latest revision as of 15:28, 26 July 2024

8kB / 16kB / 32kB / 64kBytes (28pin) ROMs

Nintendo used by default JEDEC standard compatible pinouts for all their mask ROMs of 64 kBytes and below (but some particular boards might be exceptions !). Names [in brackets] applies when the corresponding address pin is unused. On boards where an adress pin is never used (for example, A15 is never used on NROM boards as the ROM can't be greater than 32k), what is in brackets connects to the unused pin.

For some unknown reasons, unused address lines on smaller ROMs had to be put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though. As Nintendo liked to use Mask ROMs from various manufacturers, apparently unused pins could be either not connected or additional active high CE enable lines. This would ensure that if Nintendo would order mask ROMs with additional enable lines that aren't used, they could place them on the board without having the fear of having them disabled accidentally.

This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind. Probably as the game will work if the ROM is "accidentally" disabled before the first write to CHR bankswitching registers.

  27C64/128/256/512 EPROM pinout

              ---_---
 [+5V] A15 - |01   28| - +5V
       A12 - |02   27| - A14 [PGM]
       A7  - |03   26| - A13 [NC]
       A6  - |04   25| - A8
       A5  - |05   24| - A9
       A4  - |06   23| - A11
       A3  - |07   22| - /OE
       A2  - |08   21| - A10
       A1  - |09   20| - /CE
       A0  - |10   19| - D7
       D0  - |11   18| - D6
       D1  - |12   17| - D5
       D2  - |13   16| - D4
       GND - |14   15| - D3
              -------

128/256/512 KBytes (28/32pin) ROMs

Nintendo used the standard pinout for (extremely rare) prototype boards intended to take a 27C010/020/040 EPROM. But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not compatible. This pinout, with reshuffled enable lines and higher address lines, allows a 32-pin hole to take a 28-pin 128 KiB PRG ROM in pin 3 to pin 30.

For games using 256 KiB and larger ROMs, other companies producing Famicom or NES boards used either epoxy blobs or standard EPROM pinout. But games with 128 KiB of PRG were more often in a 28-pin package than not.

On Nintendo's boards where PRG A18 is never used, pin 2 is connected with pin 22.

Nintendo's MMC5 boards use the same pinout for both PRG and CHR ROMs, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin.

        CHR ROM, PRG ROM, and 27C010/020/040/080 EPROM pinouts compared
 
 MMC5    CHR        PRG      EPROM                   EPROM        PRG   CHR   MMC5
                                         ---_---
 A17    A17 [+5V]  A17      [VPP] A19 - |01   32| - +5V
 A18    /OE        A18 [/CE]      A16 - |02   31| - A18 [PGM]    +5V    /CE    /CE
                                  A15 - |03   30| - A17 [NC]     +5V    +5V    A19
                                  A12 - |04   29| - A14
                                  A7  - |05   28| - A13
                                  A6  - |06   27| - A8
                                  A5  - |07   26| - A9
                                  A4  - |08   25| - A11
                                  A3  - |09   24| - /OE          A16    A16    A16
                                  A2  - |10   23| - A10
                                  A1  - |11   22| - /CE                 GND
                                  A0  - |12   21| - D7
                                  D0  - |13   20| - D6
                                  D1  - |14   19| - D5
                                  D2  - |15   18| - D4
                                  GND - |16   17| - D3
                                         -------

PRG and CHR pins are listed only if they differ from EPROM.

Variants

Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold).

Nintendo RROM CHR ROM pinout - 8 KBytes (28pin)

This particular board is functionally identical to NROM but with a strange CHR pinout :

  RROM Non-standard 64-kbit CHR pinout
             ---_---
      A7  - |01   28| - +5V
      A6  - |02   27| - A8
      A5  - |03   26| - A9
      A4  - |04   25| - A12
      A3  - |05   24| - /CE
      +5V - |06   23| - NC
      +5V - |07   22| - /OE
      A2  - |08   21| - A10
      A1  - |09   20| - A11
      A0  - |10   19| - D7
      D0  - |11   18| - D6
      D1  - |12   17| - D5
      D2  - |13   16| - D4
      GND - |14   15| - D3
             -------

Nintendo SROM CHR ROM pinout - 8 KBytes (24pin)

This particular board is functionally identical to NROM but the CHR uses a 24-pin 8KB ROM with pinout very similar to the 27C32:

  SROM  23C62/64 JEDEC-Standard 64-kbit CHR pinout
            ---_---
      A7 - |01   24| - Vcc
      A6 - |02   23| - A8
      A5 - |03   22| - A9
      A4 - |04   21| - A12
      A3 - |05   20| - /OE
      A2 - |06   19| - A10
      A1 - |07   18| - A11
      A0 - |08   17| - D7
      D0 - |09   16| - D6
      D1 - |10   15| - D5
      D2 - |11   14| - D4
     Gnd - |12   13| - D3
            -------

With only one output enable, the board synthesizes the signal (/OE = PPU A13 + PPU /RD) using two transistors and a resistor.

Nintendo STROM

This board uses three 23C62, 8 KBytes, 24 pin MASK ROMs (two as PRG-ROM and one as CHR-ROM) and a few discrete elements for an address decoder [1]

Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin)

Very slight variant of the standard PRG-ROM pinout above, where an additional active high enable line is used to prevent bus conflicts.

              ---_---
       A17 - |01   32| - +5V
       /CE - |02   31| - CE (R/W)
       A15 - |03   30| - +5V
       A12 - |04   29| - A14
       A7  - |05   28| - A13
       A6  - |06   27| - A8 
       A5  - |07   26| - A9
       A4  - |08   25| - A11
       A3  - |09   24| - A16
       A2  - |10   23| - A10
       A1  - |11   22| - /CE
       A0  - |12   21| - D7
       D0  - |13   20| - D6
       D1  - |14   19| - D5
       D2  - |15   18| - D4
      GND  - |16   17| - D3
              -------

Japanese After Burner connects two such 128 kB mask roms in parallel (pin 2 = PPU /RD, pin 22 = SS4-CHR-/CE, pin31 = SS4-CHR-A17), which implies that one of them needs to have pin 31 active low and the other active high. [2]

Signal descriptions

A0-A12
address
D0-D7
data
/CE, /OE
The ROM will output data at address A on pins D only if all its CE (chip enable) and OE (output enable) pins are active (CE active high, /CE active low). /CE is sometimes called /CS (chip select). A memory responds faster to /OE than to /CE but draws less current while /CE is not asserted.
PGM, VPP
Used only during EPROM programing / erasing process.

See Cartridge connector for other signals descriptions.

Converting a donor board

To convert a cartridge board to accept EPROM:

  1. Compare the pinout of your EPROM to the mask ROM pinout expected by the board.
  2. Lift any pins whose signals differ.
  3. Solder short wires to the corresponding holes.
  4. Solder down the memory or socket with the pins that do not differ.
  5. Solder each lifted pin to the hole with the same signal.

See also