IRQ: Difference between revisions
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'''IRQ''' ( | '''IRQ''' (interrupt request) is a signal on the NES CPU. It is used to trigger a [[CPU interrupts|CPU interrupt]]. | ||
If the CPU's /IRQ input is 0 at the end of an instruction, the CPU pushes the program counter and the processor status register, | If the CPU's /IRQ input is 0 at the end of an instruction, then the CPU pushes the program counter and the processor status register, sets the I flag to ignore further IRQs, and the Program Counter takes the value read at $fffe and $ffff. | ||
This behaviour is masked by the CPU's interrupt-disable [[status flag]]. The SEI instruction disables IRQs, and the CLI instruction enables them. | |||
/IRQ functions as an open collector input: it is normally 1, but any device on the CPU bus can pull it down to 0. | /IRQ functions as an open collector input: it is normally 1, but any device on the CPU bus can pull it down to 0. | ||
An IRQ handler is expected to push any registers it uses, acknowledge the interrupt by writing to a port so that the source no longer forces /IRQ to 0 | An IRQ handler is expected to push any registers it uses, acknowledge the interrupt by writing to a port so that the source no longer forces /IRQ to 0, pull the registers back, and return with RTI. | ||
Therefore if a program uses more than one source of IRQ, the priority between the conflicting interrupts should be handled in software. | |||
Sources of IRQ on a Famicom or NES include | Sources of IRQ on a Famicom or NES include | ||
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! Source || Enable || Disable || Acknowledge | ! Source || Enable || Disable || Acknowledge | ||
|- | |- | ||
| [[APU DMC]] finish || $4010 write with bit 7 = 1 || $4010 write otherwise || Disable then reenable | | [[APU DMC]] finish || $4010 write with bit 7 = 1 || $4010 write otherwise || Disable then reenable, or [[APU Status]] ($4015) write | ||
|- | |- | ||
| [[APU Frame Counter]] || $4017 write with bits 7-6 = 00 || $4017 write otherwise || [[APU Status]] ($4015) read | | [[APU Frame Counter]] || $4017 write with bits 7-6 = 00 || $4017 write otherwise || [[APU Status]] ($4015) read | ||
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|- | |- | ||
| [[MMC5]] || Write $80 to $5204 || Write $00 to $5204 || Read $5204 | | [[MMC5]] || Write $80 to $5204 || Write $00 to $5204 || Read $5204 | ||
|- | |||
| [[VRC IRQ|VRC4/6/7]] || colspan=3| depends on specific IC | |||
|- | |||
| [[Sunsoft FME-7|FME-7]] || write $81 to register $D || write even number to register $D || write anything to register $D | |||
|- | |||
| [[INES Mapper 019|Namco 163]] || write to $5000 and $5800 || $5800 write with bit 7 = 0 || write to $5000 or $5800 | |||
|- | |- | ||
| [[FDS]] || Write $02 to $4022 || Write $00 to $4022 || Read $4030 | | [[FDS]] || Write $02 to $4022 || Write $00 to $4022 || Read $4030 | ||
|} | |} | ||
== See also == | |||
*[[CPU interrupts]] | |||
*[[Status flags]] used to enable/disable IRQs. | |||
*[[MMC]], common source of cartridge IRQs | |||
*[[NMI]], the other interrupt signal on the CPU | |||
Latest revision as of 17:00, 4 June 2024
IRQ (interrupt request) is a signal on the NES CPU. It is used to trigger a CPU interrupt.
If the CPU's /IRQ input is 0 at the end of an instruction, then the CPU pushes the program counter and the processor status register, sets the I flag to ignore further IRQs, and the Program Counter takes the value read at $fffe and $ffff.
This behaviour is masked by the CPU's interrupt-disable status flag. The SEI instruction disables IRQs, and the CLI instruction enables them.
/IRQ functions as an open collector input: it is normally 1, but any device on the CPU bus can pull it down to 0. An IRQ handler is expected to push any registers it uses, acknowledge the interrupt by writing to a port so that the source no longer forces /IRQ to 0, pull the registers back, and return with RTI.
Therefore if a program uses more than one source of IRQ, the priority between the conflicting interrupts should be handled in software.
Sources of IRQ on a Famicom or NES include
| Source | Enable | Disable | Acknowledge |
|---|---|---|---|
| APU DMC finish | $4010 write with bit 7 = 1 | $4010 write otherwise | Disable then reenable, or APU Status ($4015) write |
| APU Frame Counter | $4017 write with bits 7-6 = 00 | $4017 write otherwise | APU Status ($4015) read |
| MMC3 | Write to $E001 | Write to $E000 | Disable then reenable |
| MMC5 | Write $80 to $5204 | Write $00 to $5204 | Read $5204 |
| VRC4/6/7 | depends on specific IC | ||
| FME-7 | write $81 to register $D | write even number to register $D | write anything to register $D |
| Namco 163 | write to $5000 and $5800 | $5800 write with bit 7 = 0 | write to $5000 or $5800 |
| FDS | Write $02 to $4022 | Write $00 to $4022 | Read $4030 |
See also
- CPU interrupts
- Status flags used to enable/disable IRQs.
- MMC, common source of cartridge IRQs
- NMI, the other interrupt signal on the CPU
