6502 cycle times: Difference between revisions
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I put this spreadsheet together because I didn't like the way the timing information was organized in other places. Some mnemonic/addressing mode combinations do not have an opcode and are | I put this spreadsheet together because I didn't like the way the timing information was organized in other places. Some mnemonic/addressing mode combinations do not have an opcode and are left blank because they are not legal instructions. I may add the illegal opcodes later. Cells marked with "+" mean add one cycle if a page boundary is crossed. | ||
{| class="wikitable" | {| class="wikitable sortable" | ||
|- | |- | ||
!Mnemonic | |||
!Description | |||
!IMP | |||
!IMM | |||
!ZP | |||
!ZP,X | |||
!ZP,Y | |||
!ABS | |||
!ABS,X | |||
!ABS,Y | |||
!IND | |||
!IND,X | |||
!IND,Y | |||
!ACC | |||
|- | |- | ||
|ADC | |ADC | ||
|ADd with Carry | |ADd with Carry | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|AND | |AND | ||
|bitwise AND with accumulator | |bitwise AND with accumulator | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|ASL | |ASL | ||
|Arithmetic Shift Left | |Arithmetic Shift Left | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|BIT | |BIT | ||
|test BITs | |test BITs | ||
| | | | ||
| | | | ||
|3 | |3 | ||
| | | | ||
| | | | ||
|4 | |4 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|BRK | |BRK | ||
|BreaK | |BreaK | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|CMP | |CMP | ||
|CoMPare accumulator | |CoMPare accumulator | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|CPX | |CPX | ||
|ComPare X register | |ComPare X register | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
| | | | ||
| | | | ||
|4 | |4 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|CPY | |CPY | ||
|ComPare Y register | |ComPare Y register | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
| | | | ||
| | | | ||
|4 | |4 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|DEC | |DEC | ||
|DECrement memory | |DECrement memory | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|EOR | |EOR | ||
|bitwise Exclusive OR | |bitwise Exclusive OR | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|INC | |INC | ||
|INCrement memory | |INCrement memory | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|JMP | |JMP | ||
|JuMP | |JuMP | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|3 | |3 | ||
| | | | ||
| | | | ||
|5 | |5 | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|JSR | |JSR | ||
|Jump to SubRoutine | |Jump to SubRoutine | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|6 | |6 | ||
| | | | ||
| | | | ||
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| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|LDA | |LDA | ||
|LoaD Accumulator | |LoaD Accumulator | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|LDX | |LDX | ||
|LoaD X register | |LoaD X register | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
| | | | ||
|4 | |4 | ||
|4 | |4 | ||
| | | | ||
|4+ | |4+ | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|LDY | |LDY | ||
|LoaD Y register | |LoaD Y register | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
| | | | ||
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| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
|LSR | |LSR | ||
|Logical Shift Right | |Logical Shift Right | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|2 | |2 | ||
|- | |- | ||
|NOP | |NOP | ||
|No | |No OPeration | ||
|2 | |2 | ||
| | | | ||
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|- | |- | ||
|ORA | |ORA | ||
|bitwise OR with Accumulator | |bitwise OR with Accumulator | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|ROL | |ROL | ||
|Rotate Left | |Rotate Left | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
| | | | ||
| | | | ||
| | | | ||
|2 | |2 | ||
|- | |- | ||
|ROR | |ROR | ||
|Rotate Right | |Rotate Right | ||
| | | | ||
| | | | ||
|5 | |5 | ||
|6 | |6 | ||
| | | | ||
|6 | |6 | ||
|7 | |7 | ||
| | | | ||
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|2 | |2 | ||
|- | |- | ||
Line 336: | Line 336: | ||
|ReTurn from Interrupt | |ReTurn from Interrupt | ||
|6 | |6 | ||
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|- | |- | ||
|RTS | |RTS | ||
|ReTurn from Subroutine | |ReTurn from Subroutine | ||
|6 | |6 | ||
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|- | |- | ||
|SBC | |SBC | ||
|SuBtract with Carry | |SuBtract with Carry | ||
| | | | ||
|2 | |2 | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|4+ | |4+ | ||
|4+ | |4+ | ||
| | | | ||
|6 | |6 | ||
|5+ | |5+ | ||
| | | | ||
|- | |- | ||
|STA | |STA | ||
|Store Accumulator | |Store Accumulator | ||
| | | | ||
| | | | ||
|3 | |3 | ||
|4 | |4 | ||
| | | | ||
|4 | |4 | ||
|5 | |5 | ||
|5 | |5 | ||
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|6 | |6 | ||
|6 | |6 | ||
| | | | ||
|- | |- | ||
|STX | |STX | ||
|Store X register | |Store X register | ||
| | | | ||
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|3 | |3 | ||
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|4 | |4 | ||
|4 | |4 | ||
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|- | |- | ||
|STY | |STY | ||
|Store Y register | |Store Y register | ||
| | | | ||
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|3 | |3 | ||
|4 | |4 | ||
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|4 | |4 | ||
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|- | |- | ||
|TAX | |TAX | ||
|Transfer A to X | |Transfer A to X | ||
|2 | |2 | ||
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|- | |- | ||
|TXA | |TXA | ||
|Transfer X to A | |Transfer X to A | ||
|2 | |2 | ||
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|- | |- | ||
|DEX | |DEX | ||
|DEcrement X | |DEcrement X | ||
|2 | |2 | ||
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|- | |- | ||
|INX | |INX | ||
|INcrement X | |INcrement X | ||
|2 | |2 | ||
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|- | |- | ||
|TAY | |TAY | ||
|Transfer A to Y | |Transfer A to Y | ||
|2 | |2 | ||
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|- | |- | ||
|TYA | |TYA | ||
|Transfer Y to A | |Transfer Y to A | ||
|2 | |2 | ||
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|- | |- | ||
|DEY | |DEY | ||
|Decrement Y | |Decrement Y | ||
|2 | |2 | ||
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|- | |- | ||
|INY | |INY | ||
|Increment Y | |Increment Y | ||
|2 | |2 | ||
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|- | |- | ||
|CLC | |CLC | ||
|CLear Carry | |CLear Carry | ||
|2 | |2 | ||
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|- | |- | ||
|SEC | |SEC | ||
|SEt Carry | |SEt Carry | ||
|2 | |2 | ||
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|- | |- | ||
|CLI | |CLI | ||
|CLear Interrupt | |CLear Interrupt | ||
|2 | |2 | ||
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|- | |- | ||
|SEI | |SEI | ||
|SEt Interrupt | |SEt Interrupt | ||
|2 | |2 | ||
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|- | |- | ||
|CLV | |CLV | ||
|CLear oVerflow | |CLear oVerflow | ||
|2 | |2 | ||
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|- | |- | ||
|CLD | |CLD | ||
|CLear Decimal | |CLear Decimal | ||
|2 | |2 | ||
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|- | |- | ||
|SED | |SED | ||
|SEt Decimal | |SEt Decimal | ||
|2 | |2 | ||
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|- | |- | ||
|} | |} |
Latest revision as of 18:12, 16 November 2021
I put this spreadsheet together because I didn't like the way the timing information was organized in other places. Some mnemonic/addressing mode combinations do not have an opcode and are left blank because they are not legal instructions. I may add the illegal opcodes later. Cells marked with "+" mean add one cycle if a page boundary is crossed.
Mnemonic | Description | IMP | IMM | ZP | ZP,X | ZP,Y | ABS | ABS,X | ABS,Y | IND | IND,X | IND,Y | ACC |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADC | ADd with Carry | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
AND | bitwise AND with accumulator | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
ASL | Arithmetic Shift Left | 5 | 6 | 6 | 7 | ||||||||
BIT | test BITs | 3 | 4 | ||||||||||
BRK | BreaK | 7 | |||||||||||
CMP | CoMPare accumulator | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
CPX | ComPare X register | 2 | 3 | 4 | |||||||||
CPY | ComPare Y register | 2 | 3 | 4 | |||||||||
DEC | DECrement memory | 5 | 6 | 6 | 7 | ||||||||
EOR | bitwise Exclusive OR | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
INC | INCrement memory | 5 | 6 | 6 | 7 | ||||||||
JMP | JuMP | 3 | 5 | ||||||||||
JSR | Jump to SubRoutine | 6 | |||||||||||
LDA | LoaD Accumulator | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
LDX | LoaD X register | 2 | 3 | 4 | 4 | 4+ | |||||||
LDY | LoaD Y register | 2 | 3 | 4 | 4 | 4+ | |||||||
LSR | Logical Shift Right | 5 | 6 | 6 | 7 | 2 | |||||||
NOP | No OPeration | 2 | |||||||||||
ORA | bitwise OR with Accumulator | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
ROL | Rotate Left | 5 | 6 | 6 | 7 | 2 | |||||||
ROR | Rotate Right | 5 | 6 | 6 | 7 | 2 | |||||||
RTI | ReTurn from Interrupt | 6 | |||||||||||
RTS | ReTurn from Subroutine | 6 | |||||||||||
SBC | SuBtract with Carry | 2 | 3 | 4 | 4 | 4+ | 4+ | 6 | 5+ | ||||
STA | Store Accumulator | 3 | 4 | 4 | 5 | 5 | 6 | 6 | |||||
STX | Store X register | 3 | 4 | 4 | |||||||||
STY | Store Y register | 3 | 4 | 4 | |||||||||
TAX | Transfer A to X | 2 | |||||||||||
TXA | Transfer X to A | 2 | |||||||||||
DEX | DEcrement X | 2 | |||||||||||
INX | INcrement X | 2 | |||||||||||
TAY | Transfer A to Y | 2 | |||||||||||
TYA | Transfer Y to A | 2 | |||||||||||
DEY | Decrement Y | 2 | |||||||||||
INY | Increment Y | 2 | |||||||||||
CLC | CLear Carry | 2 | |||||||||||
SEC | SEt Carry | 2 | |||||||||||
CLI | CLear Interrupt | 2 | |||||||||||
SEI | SEt Interrupt | 2 | |||||||||||
CLV | CLear oVerflow | 2 | |||||||||||
CLD | CLear Decimal | 2 | |||||||||||
SED | SEt Decimal | 2 |