Talk:INES Mapper 047: Difference between revisions
From NESdev Wiki
Jump to navigationJump to search
(→Oversize definition: new section) |
(→Oversize definition: Competing) |
||
| Line 2: | Line 2: | ||
It would be nice to define this as "the latch controls the MSB of both PRG and CHR addresses" instead of always A17. This would make it trivial to get a RAMless oversize MMC3 with 1MiB PRG and 512KiB CHR. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 02:18, 15 September 2013 (MDT) | It would be nice to define this as "the latch controls the MSB of both PRG and CHR addresses" instead of always A17. This would make it trivial to get a RAMless oversize MMC3 with 1MiB PRG and 512KiB CHR. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 02:18, 15 September 2013 (MDT) | ||
:A competing oversize definition would be to keep each segment 128K and add more bits to the latch. For example 4 bits would give 16 banks, or 2 MiB PRG and 2 MiB CHR. --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 06:41, 15 September 2013 (MDT) | |||
