Wouldn't it be better to just define component names for the cart edge, ROMs, RAMs, and CIC for a Verilog description of a mapper to use? --Tepples (talk) 17:08, 15 July 2016 (MDT)
It did strike me that way. This was an idea I should have sat on and brewed longer. Odds are I'll just end up making macros/a program to write the output file(s) instead of making a whole language. —Myask (talk) 18:26, 19 July 2016 (MDT)
