Mask ROM pinout

8kB / 16kB / 32kB / 64kBytes (28pin) ROMs

Nintendo used by default JEDEC standard compatible pinout for all their mask ROMs of 64 kByes and below. Names [in brackets] applies when the corresponding address pin is unused. On boards where an adress pin is never used (for example, A15 is never used on NROM boards as the ROM can't be greater than 32k), what is in brackets connects to the unused pin.

For some unknown reasons, unused address lines on smaller ROMs had to be put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though.

This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind.

   27C64/128/256/512 EPROM pinout
 
               ---_---
  [+5V] A15 - |01   28| - +5V
        A12 - |02   27| - A14 [PGM]
        A7  - |03   26| - A13 [NC]
        A6  - |04   25| - A8
        A5  - |05   24| - A9
        A4  - |06   23| - A11
        A3  - |07   22| - /OE
        A2  - |08   21| - A10
        A1  - |09   20| - /CE
        A0  - |10   19| - D7
        D0  - |11   18| - D6
        D1  - |12   17| - D5
        D2  - |13   16| - D4
        GND - |14   15| - D3
               -------

               PRG ROM pinout
 
                  ---_---
 [+5V] PRG A15 - |01   28| - +5V
       PRG A12 - |02   27| - PRG A14 [+5V]
       PRG A7  - |03   26| - PRG A13 [N/C]
       PRG A6  - |04   25| - PRG A8
       PRG A5  - |05   24| - PRG A9
       PRG A4  - |06   23| - PRG A11
       PRG A3  - |07   22| - PRG /CE
       PRG A2  - |08   21| - PRG A10
       PRG A1  - |09   20| - GND
       PRG A0  - |10   19| - PRG D7
       PRG D0  - |11   18| - PRG D6
       PRG D1  - |12   17| - PRG D5
       PRG D2  - |13   16| - PRG D4
       GND     - |14   15| - PRG D3
                  -------

               CHR ROM pinout
 
                  ---_---
       +5V     - |01   28| - +5V
       CHR A12 - |02   27| - PRG A14
       CHR A7  - |03   26| - PRG A13
       CHR A6  - |04   25| - CHR A8
       CHR A5  - |05   24| - CHR A9
       CHR A4  - |06   23| - CHR A11
       CHR A3  - |07   22| - /OE (CHR /RD)
       CHR A2  - |08   21| - CHR A10
       CHR A1  - |09   20| - /CE (CHR A13)
       CHR A0  - |10   19| - CHR D7
       CHR D0  - |11   18| - CHR D6
       CHR D1  - |12   17| - CHR D5
       CHR D2  - |13   16| - CHR D4
       GND     - |14   15| - CHR D3
                  -------

128/256/512 KBytes (28/32pin) ROMs

Nintendo used for the vast majority of their boards a different pinout which is not JEDEC compatible. The location of enable lines and higher address lines is changed (highlighted in bold). This system allows 128 KB PRG ROMs are only 28 pins, they are shuffled 2 pins down, starting from pin 3 to pin 30.

All known non-Nintendo made boards with ROMs of those sizes that aren't made of Epoxy blobs uses a 27C010/020/040 EPROM compatible pinouts. Nintendo also made boards with such compatible pinouts, but they only exists in prototypes, and therefore are extremely rare.

On boards where PRG A18 is never used, pin 2 is connected with pin 22.

27C010/020/040/80 EPROM pinout ---_--- [VPP] A19 - |01 32| - +5V A16 - |02 31| - A18 [PGM] A15 - |03 30| - A17 [NC] A12 - |04 29| - A14 A7 - |05 28| - A13 A6 - |06 27| - A8 A5 - |07 26| - A9 A4 - |08 25| - A11 A3 - |09 24| - /OE A2 - |10 23| - A10 A1 - |11 22| - /CE A0 - |12 21| - D7 D0 - |13 20| - D6 D1 - |14 19| - D5 D2 - |15 18| - D4 GND - |16 17| - D3 -------

Nintendo PRG ROM pinout ---_--- PRG A17 - |01 32| - +5V [/CE] PRG A18 - |02 31| - +5V PRG A15 - |03 30| - +5V PRG A12 - |04 29| - PRG A14 PRG A7 - |05 28| - PRG A13 PRG A6 - |06 27| - PRG A8 PRG A5 - |07 26| - PRG A9 PRG A4 - |08 25| - PRG A11 PRG A3 - |09 24| - PRG A16 PRG A2 - |10 23| - PRG A10 PRG A1 - |11 22| - PRG /CE PRG A0 - |12 21| - PRG D7 PRG D0 - |13 20| - PRG D6 PRG D1 - |14 19| - PRG D5 PRG D2 - |15 18| - PRG D4 GND - |16 17| - PRG D3 -------

Nintendo CHR ROM pinout ---_--- [+5V] CHR A17 - |01 32| - +5V (CHR /RD) /OE - |02 31| - /CE (CHR A13) CHR A15 - |03 30| - +5V CHR A12 - |04 29| - CHR A14 CHR A7 - |05 28| - CHR A13 CHR A6 - |06 27| - CHR A8 CHR A5 - |07 26| - CHR A9 CHR A4 - |08 25| - CHR A11 CHR A3 - |09 24| - CHR A16 CHR A2 - |10 23| - CHR A10 CHR A1 - |11 22| - GND (/OE ?) CHR A0 - |12 21| - CHR D7 CHR D0 - |13 20| - CHR D6 CHR D1 - |14 19| - CHR D5 CHR D2 - |15 18| - CHR D4 GND - |16 17| - CHR D3 -------

Variants

Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold).

Nintendo MMC5 PRG/CHR ROM pinouts - 128/256/512/1024 kBytes (32pin)

Variant of Nintendo's pinouts just above for MMC5 boards which supports up to 1MB of data. Both PRG and CHR ROMs are the same pinout, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin.

Nintendo MMC5 PRG ROM pinout ----_---- PRG A17 - |01 32| - +5V PRG A18 - |02 31| - PRG /CE PRG A15 - |03 30| - PRG A19 PRG A12 - |04 29| - PRG A14 PRG A7 - |05 28| - PRG A13 PRG A6 - |06 27| - PRG A8 PRG A5 - |07 26| - PRG A9 PRG A4 - |08 25| - PRG A11 PRG A3 - |09 24| - PRG A16 PRG A2 - |10 23| - PRG A10 PRG A1 - |11 22| - /OE (GND) PRG A0 - |12 21| - PRG D7 PRG D0 - |13 20| - PRG D6 PRG D1 - |14 19| - PRG D5 PRG D2 - |15 18| - PRG D4 GND - |16 17| - PRG D3 -------

Nintendo MMC5 CHR ROM pinout ----_---- CHR A17 - |01 32| - +5V CHR A18 - |02 31| - /CE (CHR A13) CHR A15 - |03 30| - CHR A19 CHR A12 - |04 29| - CHR A14 CHR A7 - |05 28| - CHR A13 CHR A6 - |06 27| - CHR A8 CHR A5 - |07 26| - CHR A9 CHR A4 - |08 25| - CHR A11 CHR A3 - |09 24| - CHR A16 CHR A2 - |10 23| - CHR A10 CHR A1 - |11 22| - /OE (CHR /RD) CHR A0 - |12 21| - CHR D7 CHR D0 - |13 20| - CHR D6 CHR D1 - |14 19| - CHR D5 CHR D2 - |15 18| - CHR D4 GND - |16 17| - CHR D3 -------

Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin)

Very slight variant of the standard PRG-ROM pinout above, where an additional active high enable line is used to prevent bus conflicts.

                 ---_---
      PRG A17 - |01   32| - +5V
      PRG /CE - |02   31| - CE (R/W)
      PRG A15 - |03   30| - +5V
      PRG A12 - |04   29| - PRG A14
      PRG A7  - |05   28| - PRG A13
      PRG A6  - |06   27| - PRG A8 
      PRG A5  - |07   26| - PRG A9
      PRG A4  - |08   25| - PRG A11
      PRG A3  - |09   24| - PRG A16
      PRG A2  - |10   23| - PRG A10
      PRG A1  - |11   22| - PRG /CE
      PRG A0  - |12   21| - PRG D7
      PRG D0  - |13   20| - PRG D6
      PRG D1  - |14   19| - PRG D5
      PRG D2  - |15   18| - PRG D4
      GND     - |16   17| - PRG D3
                 -------

Signal descriptions

A0-A12

address

D0-D7

data

/CE, /OE

The ROM will output data at adress A on pins D only if all it's CE and OE pins are active (CE active high, /CE active low).

PGM, VPP

Used only during EPROM programing / erasing process.

See here for other signals descriptions.