IRQ

IRQ (Interrupt request) is a signal on the NES CPU.

If the CPU's /IRQ input is 0 at the end of an instruction, the CPU pushes the program counter and the processor status register, does SEI to ignore further IRQs, and finally JMP ($FFFE).

/IRQ functions as an open collector input: it is normally 1, but any device on the CPU bus can pull it down to 0. An IRQ handler is expected to push any registers it uses, acknowledge the interrupt by writing to a port so that the source no longer forces /IRQ to 0), pull the registers back, and return with RTI.

Sources of IRQ on a Famicom or NES include

Source	Enable	Disable	Acknowledge
APU DMC finish	$4010 write with bit 7 = 1	$4010 write otherwise	Disable then reenable, or $4015 write
APU Frame Counter	$4017 write with bits 7-6 = 00	$4017 write otherwise	APU Status ($4015) read
MMC3	Write to $E001	Write to $E000	Disable then reenable
MMC5	Write $80 to $5204	Write $00 to $5204	Read $5204
FDS	Write $02 to $4022	Write $00 to $4022	Read $4030

See also

• MMC, common source of cartridge IRQs
• NMI, the other interrupt signal on the CPU