CPU power up state

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Revision as of 08:41, 20 March 2024 by Lidnariq (talk | contribs) (→‎At power-up: P is not 8 bits wide. Don't define the other two bits because they don't exist.)
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The following results are from a US (NTSC) NES, original front-loading design, RP2A03G CPU chip, NES-CPU-07 main board revision, manufactured in 1988. The memory values are probably slightly different for each individual NES console. Please note that you should NOT rely on the state of any registers after Power-UP and especially not the stack register and RAM ($0000-$07FF).

At power-up

Status: Carry, Zero, Decimal, Overflow, Negative clear. Interrupt Disable set.
A, X, Y = 0
S = $FD[1]
$4017 = $00 (frame irq enabled)
$4015 = $00 (all channels disabled)
$4000-$400F = $00
$4010-$4013 = $00 [2]
All 15 bits of noise channel LFSR = $0000[3]. The first time the LFSR is clocked from the all-0s state, it will shift in a 1.
APU Frame Counter:
2A03E, G, various clones: APU Frame Counter reset.
2A03letterless: APU frame counter powers up at a value equivalent to 15
Internal memory ($0000-$07FF) has unreliable startup state. Some machines may have consistent RAM contents at power-on, but others do not.
  • Emulators often implement a consistent RAM startup state (e.g. all $00 or $FF, or a particular pattern), and flash carts like the PowerPak may partially or fully initialize RAM before starting a program, so an NES programmer must be careful not to rely on the startup contents of RAM.

After reset

A, X, Y were not affected
S was decremented by 3 (but nothing was written to the stack)[1]
The I (IRQ disable) flag was set to true (status ORed with $04)
The internal memory was unchanged
APU mode in $4017 was unchanged
APU was silenced ($4015 = 0)
APU triangle phase is reset to 0 (i.e. outputs a value of 15, the first step of its waveform)
APU DPCM output ANDed with 1 (upper 6 bits cleared)
APU Frame Counter:
2A03E, G, various clones: APU Frame Counter reset.
2A03letterless: APU frame counter retains old value [4]

See also

Notes

  1. ↑ 1.0 1.1 RESET uses the logic shared with NMI, IRQ, and BRK that would push PC and P. However, like some but not all 6502s, the 2A03 prohibits writes during reset. This test relies on open bus being precharged by these reads. See 27c3: Reverse Engineering the MOS 6502 CPU (en) from 41:45 onward for details
  2. ↑ Eliminator Boat Duel
  3. ↑ Noise channel init log
  4. ↑ 2A03letterless is missing transistor to set frame counter LFSR on reset
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