Visual6502wiki/6502 Stack Register High Bits
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A series of aligned photographs of the chip surface, chip substrate, and polygon model.
File:Stack reg high2 top.jpg Chip surface |
File:Stack reg high2 sub.jpg Chip substrate showing conductive substrate regions |
File:Stack reg high2 vec.jpg Vector polygons representing chip features. The purple trace carries one phase of the clock |
File:Stack reg high2 subTied.jpg Conductive substrate tied to ground (green), +5V (red), or floating (yellow), with transistors (purple) |
File:Stack reg high2 SPVTB.jpg Vector polygons over the chip substrate image |
6507D register section
A series of aligned photographs: brightfield, brightfield with crossed polarizers, darkfield
File:6507 20x top-000000r.jpg 6507, 20x objective, brightfield |
File:6507 20x top-000003r.jpg 6507, 20x objective, brightfield, partly crossed pol |
File:6507 20x top-000004r.jpg 6507, 20x objective, brightfield, 90 deg pol |
File:6507 20x top-000007r.jpg 6507, 20x objective, darkfield |
File:6507 20x top-000008r.jpg 6507, 20x objective, darkfield |
