User:Ddribin/PPU Sandbox

PPUCTRL - The PPU Control Register

Bit	7	6	5	4	3	2	1	0
$2000	NMI	MSS	SSZ	BPT	SPT	VDN	NTA1	NTA0
Read/Write	W	W	W	W	W	W	W	W
Initial Value	X	X	X	X	X	X	X	X

Bit 7 - NMI: NMI Enable

Generate an NMI at the start of th vertical blanking interval (0: off; 1: on)

Bit 6 - MSS: Master/Slave Enable

Has no effect on the NES.

Bit 5 - SSZ: Sprite Size

Sprite size (0: 8x8; 1: 8x16)

Bit 4 - BPT: Background Pattern Table

Background pattern table address (0: $0000; 1: $1000)

Bit 3 - SPT: Sprite Pattern Table

Sprite pattern table address for 8x8 sprites (0: $0000; 1: $1000)

Bit 2 - VDN: VRAM Increment Down

VRAM address increment per CPU read/write of PPUDATA (0: increment by 1, going across; 1: increment by 32, going down)

Bits 1, 0 - NTA1 and NTA0: Base Nametable Address

Base nametable address (00 = $2000; 01 = $2400; 10 = $2800; 11 = $2C00)

NTA1	NTA0	Base VRAM Address
0	0	$2000 (Nametable 0)
0	1	$2400 (Nametable 1)
1	0	$2800 (Nametable 2)
1	1	$2C00 (Nametable 3)