VRC6

The Konami's VRC6 ASIC mapper comes in two variants. The register descriptions given here are as they exist in Akumajou Densetsu (iNES Mapper 024). The A0 and A1 lines are switched in Madara and Esper Dream 2 (iNES Mapper 026), so for those games, adjustments will need to be made ($x001 becomes $x002 and vice versa).

Overview

• PRG ROM size: Up to 256 KB
• PRG ROM bank size: 16 KB at $8000, 8 KB at $C000
• PRG RAM: Up to 8 KB
• CHR capacity: Up to 256 KB ROM
• CHR bank size: 1 KB
• Nametable mirroring: Controlled by mapper
• Subject to bus conflicts: No

See VRC6 pinout for chip pinout.

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM at $C000

PPU Banking Style ($B003)

7  bit  0
---------
W.PN MMDD
| || ||||
| || ||++- PPU addressing mode; see below
| || ++--- Mirroring (0: vertical; 1: horizontal;
| ||                      2: one-screen, lower bank; 3: one-screen, upper bank)
| |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
| +------- 1: Pattern tables come from CHRROM, (0: buggy)
+--------- PRG RAM enable

In practice, all VRC6 games used the Famicom's CIRAM as the CHRRAM, like the Namco 163. A game could have been made that used a separate larger CHRRAM instead.

Nametable control in mode 0

CHRRAM A10 is connected according to the mirroring control bits.

It is not known what the MSBs of nametable registers are.

Nametable control in mode 1

The values written to $E00x specify the banks used for nametables.

Nametable control in mode 2

The value written to $E002 specifies the bank used in lieu of CIRAM $000-$3FF. The value written to $E003 specifies the bank used in lieu of CIRAM $400-$7FF. These are then placed into the nametables according to the mirroring control bits.

This behavior is identical to the Sunsoft 4 mapper.

Nametable control in mode 3

CHRRAM A10 is connected according to the mirroring control bits. For both registers mentioned below, the LSB is ignored (and pays attention to the mirroring control bits instead)

The value written to $E002 specifies a 2 KiB bank to be used for the left or top two nametables. The value written to $E003 specifies a 2 KiB bank to be used for the right or bottom two nametables.

The mirroring bits specify whether it's side-by-side or top-and-bottom:

Mirroring = 0, 8 - left and right 
          = 4, C - top and bottom

CHR Select 0…7 ($Dxxx, $Exxx)

PPU addressing mode	0	1	2 or 3
Write to CPU address	CHR banks affected
$D000	$0000-$03FF	$0000-$07FF	$0000-$03FF
$D001	$0400-$07FF	$0800-$0FFF	$0400-$07FF
$D002	$0800-$0BFF	$1000-$17FF	$0800-$0BFF
$D003	$0C00-$0FFF	$1800-$1FFF	$0C00-$0FFF
$E000	$1000-$13FF	$2000-$23FF	$1000-$17FF
$E001	$1400-$17FF	$2400-$27FF	$1800-$1FFF
$E002	$1800-$1BFF	$2800-$2BFF	see previous
$E003	$1C00-$1FFF	$2C00-$2FFF	see previous

2KiB slices always ignore the LSB, like the MMC3 does.

IRQ control ($F00x)

$F000:  IRQ Latch
$F001:  IRQ Control
$F002:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.