VRC4

The Konami VRC4 is an ASIC mapper.

Overview

PRG ROM size: Up to 256 KiB
PRG ROM bank size: 8 KiB at $A000, and $8000 OR $C000
PRG RAM: none, 2 KiB, or 8 KiB
CHR ROM size: Up to 512 KiB
CHR bank size: 1 KiB
Nametable mirroring: Controlled by mapper
Subject to bus conflicts: No

The Konami VRC4 is almost identical to the VRC2, but with a bit more capabilities, such as the option to swap PRG at $C000 instead of $8000 and an IRQ counter.

See VRC4 pinout for chip pinout.

Banks

CPU $6000-$6FFF: optional 2 KiB PRG RAM bank (mirrored once), or
CPU $6000-$7FFF: optional 8 KiB PRG RAM bank
CPU $8000-$9FFF (or $C000-$DFFF): 8 KiB switchable PRG ROM bank
CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
CPU $C000-$DFFF (or $8000-$9FFF): 8 KiB PRG ROM bank, fixed to the second-last bank
CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank
PPU $0000-$03FF: 1 KiB switchable CHR bank
PPU $0400-$07FF: 1 KiB switchable CHR bank
PPU $0800-$0BFF: 1 KiB switchable CHR bank
PPU $0C00-$0FFF: 1 KiB switchable CHR bank
PPU $1000-$13FF: 1 KiB switchable CHR bank
PPU $1400-$17FF: 1 KiB switchable CHR bank
PPU $1800-$1BFF: 1 KiB switchable CHR bank
PPU $1C00-$1FFF: 1 KiB switchable CHR bank

Revisions

This mapper has been used with several board revisions, each of which uses different address lines. All boards use A15-A12 the same way, along with two lines from A7-A0. Here is a listing of known revisions, which address lines are used, and which iNES mapper number is used to represent it:

variant   lines     registers                       iNES Mapper Number
----------------------------------------------------------------------
VRC4a     A1, A2    $x000, $x002, $x004, $x006      021
VRC4b     A1, A0    $x000, $x002, $x001, $x003      025
VRC4c     A6, A7    $x000, $x040, $x080, $x0C0      021
VRC4d     A3, A2    $x000, $x008, $x004, $x00C      025
VRC4e     A2, A3    $x000, $x004, $x008, $x00C      023
VRC4 #27  A0, A1    $x000, $x001, $x002, $x003      027

Some variants that use the same address lines use them in different ways. For example, VRC4d and VRC4e both use A2 and A3, however VRC4d has them reversed.

For historical reasons, some variants share a mapper number. These may be detected with a hash of the PRG ROM, or the address lines used may be expressed in NES 2.0 with submappers.

The RAM decoding circuit that's part of the VRC4 itself only decodes RAM from $6000-$6FFF. For the one game with 8 KiB of RAM, an external circuit was added.

Registers

This page lists registers as they are in the VRC4a variant. For other variants, you can use the diagram above for determining which registers are used.

PRG Swap Mode control ($9004, $9006)

7  bit  0
---------
.... ..M.
       |
       +-- Swap Mode

When 'M' is clear:

the 8 KiB page at $8000 is controlled by the $800x register
the 8 KiB page at $C000 is fixed to the second last 8 KiB in the ROM

When 'M' is set:

the 8 KiB page at $8000 is fixed to the second last 8 KiB in the ROM
the 8 KiB page at $C000 is controlled by the $800x register

PRG Select 0 ($8000, $8002, $8004, $8006)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KiB PRG bank at $8000 or $C000 depending on Swap Mode

PRG Select 1 ($A000, $A002, $A004, $A006)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KiB PRG bank at $A000

Mirroring Control ($9000, $9002)

7  bit  0
---------
.... ..MM
       ||
       ++- Mirroring (0: vertical; 1: horizontal;
                          2: one-screen, lower bank; 3: one-screen, upper bank;)

CHR Select 0 ($B000 + $B002)

  $B000        $B002
7  bit  0    7  bit  0
---------    ---------
.... LLLL    ...H HHHH
     ||||       | ||||
     ||||       +-++++- High 5 bits of 1 KiB CHR bank at PPU $0000
     ++++-------------- Low 4 bits

CHR Select 1 ($B004 + $B006)

  $B004        $B006
7  bit  0    7  bit  0
---------    ---------
.... LLLL    ...H HHHH
     ||||       | ||||
     ||||       +-++++- High 5 bits of 1 KiB CHR bank at PPU $0400
     ++++-------------- Low 4 bits

CHR Select 2…7 ($C000-$EFFF)

The other six CHR bank selects continue the pattern:

Write to CPU address
(low 4 bits)	(high 5 bits)	1KB CHR bank affected
$C000	$C002	$0800-$0BFF
$C004	$C006	$0C00-$0FFF
$D000	$D002	$1000-$13FF
$D004	$D006	$1400-$17FF
$E000	$E002	$1800-$1BFF
$E004	$E006	$1C00-$1FFF

IRQ Control ($F00x)

$F000:  IRQ Latch, low 4 bits
$F002:  IRQ Latch, high 4 bits
$F004:  IRQ Control
$F006:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

References

The CHR registers really are 9 bits: http://forums.nesdev.org/viewtopic.php?t=8569

VRC4

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