Taito TC0190 pinout

Taito TC0190: 0.6" high-density PDIP (Canonically iNES Mapper 033)

                 .--\/--.
  (s)  PRG D0 -> |01  40| -- Vcc
  (s)  PRG D1 -> |02  39| <- PRG R/W (F)
  (s)  PRG D2 -> |03  38| <- /ROMSEL (F)
  (s)  PRG D3 -> |04  37| <- M2 (F)
  (s)  PRG D4 -> |05  36| ?? NC
  (s)  PRG D5 -> |06  35| ?? NC
  (s)  PRG D6 -> |07  34| <- PPU A10 (F)
  (s)  PRG D7 -> |08  33| <- PPU A11 (F)
  (r) PRG A13 <- |09  32| <- PPU A12 (F)
  (r) PRG A14 <- |10  31| ?? GND
  (r) PRG A15 <- |11  30| -> CIRAM A10 (F)
  (r) PRG A16 <- |12  29| -> CHR A10 (r)
  (r) PRG A17 <- |13  28| -> CHR A11 (r)
  (r) PRG A18 <- |14  27| -> CHR A12 (r)
  (s)  PRG A0 -> |15  26| -> CHR A13 (r)
  (s)  PRG A1 -> |16  25| -> CHR A14 (r)
  (F) PRG A13 -> |17  24| -> CHR A15 (r)
  (F) PRG A14 -> |18  23| -> CHR A16 (r)
  (r) PRG /CE <- |19  22| -> CHR A17 (r)
          GND -- |20  21| ?? NC
                 '------'

Some boards added a PAL to the TC0190. As far as we can tell, the only purpose of the PAL was to move the mirroring control bit. This becomes a subset of iNES Mapper 048 instead:

TC0190 pin 30: (was CIRAM A10) now NC
TC0190 pin 38: (was /ROMSEL) now from PAL pin 12

                 PAL16R4
                  --\/--
  (F) /ROMSEL -> |01  20| -- Vcc
  (F) /ROMSEL -> |02  19| -> CIRAM A10 (F)
  (F) PRG R/W -> |03  18| ?? NC
  (F) PRG A14 -> |04  17| -> NC (latched value written to D6)
  (F) PRG A13 -> |05  16| -> NC
  (F)  PRG A1 -> |06  15| -> NC
  (F)  PRG A0 -> |07  14| -> NC
  (F) PPU A11 -> |08  13| <- PRG D6 (s)
  (F) PPU A10 -> |09  12| -> to TC0190 pin 38
          GND -- |10  11| <- GND (PAL /OE signal)
                  ------

PALs allow the programming of arbitrary logic functions, but in the PAL16R4, pins 1 and 11 have fixed functionality. This is why /ROMSEL is connected to both pins 1 and pin 2: pin 1 can only be used as a clock input to latch the value of D6, but /ROMSEL is also connected to pin 2 so that the PAL can fail to pass through the write to the TC0190 when the CPU writes to $E000.