User contributions for Lidnariq
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24 September 2019
- 06:1306:13, 24 September 2019 diff hist −1 m INES Mapper 056 →CHR banking control ($FC00-$FFFF): incorrect plural
- 05:3905:39, 24 September 2019 diff hist 0 VRC3 pinout emphasized the wrong pin on the KS202
- 05:3305:33, 24 September 2019 diff hist −5 m INES Mapper 142 edit-o
- 05:2905:29, 24 September 2019 diff hist −9 m INES Mapper 142 several FDS ports, not just SMB2j
- 05:2105:21, 24 September 2019 diff hist +1,715 N INES Mapper 142 create from FCEUX's source
- 05:1805:18, 24 September 2019 diff hist +71 INES Mapper 056 The same ASIC's use on INES Mapper 142 requires that the Bank Select register be at least three bits.
- 05:1105:11, 24 September 2019 diff hist +613 VRC3 pinout KS202 pinout probably belongs here?
- 03:1603:16, 24 September 2019 diff hist +1 m INES Mapper 056 →CHR banking control ($FC00-$FFFF): grammatical agreement
- 03:1603:16, 24 September 2019 diff hist +3,503 N INES Mapper 056 create from Krzysiobal's reverse-engineering notes.
19 September 2019
- 17:5017:50, 19 September 2019 diff hist +91 NES 2.0 Mapper 307 →Notes current
- 04:2204:22, 19 September 2019 diff hist +1,901 Namcot 108 family pinout add headings and several unlicensed rewired pinouts
17 September 2019
- 21:3021:30, 17 September 2019 diff hist +437 MMC1 pinout SZROM, add headings
15 September 2019
- 01:3101:31, 15 September 2019 diff hist +64 m Taito TC0350 pinout add header current
- 01:2801:28, 15 September 2019 diff hist +6 Taito TC0350 pinout other TC0xx0 parts have a CHR A18 pin, so it seems safe to assume that's what's going on with pin 38. Pin 3 is PRG A16 (JEDEC 21C fig. 3.2.1-2); given that other TC0xx0 parts have PRG A17 and PRG A18, that's probably the two N/C pins adjacent
9 September 2019
- 23:0923:09, 9 September 2019 diff hist +81 NES 2.0 Mapper 547 →CHR Banking Operation: call out that it's not an "override" but instead directly specifying a bitplane for that whole tile
- 17:1217:12, 9 September 2019 diff hist 0 Talk:NROM →CIC Diodes?: CIC reset is active high
- 17:0217:02, 9 September 2019 diff hist +491 INES Mapper 105 mention pedantic caveats
- 16:5516:55, 9 September 2019 diff hist 0 Cartridge connector →Pinout of 72-pin NES consoles and cartridges: CIC reset is active high
- 16:4716:47, 9 September 2019 diff hist +79 MMC1 pinout NES-EVENT doesn't let the MMC1 control CHR A12
5 September 2019
- 19:0319:03, 5 September 2019 diff hist +32 N VRC5 may as well make this current
30 August 2019
- 07:0407:04, 30 August 2019 diff hist −17 m NES 2.0 Mapper 547 →Character Translation Operation: interwiki
29 August 2019
- 22:4422:44, 29 August 2019 diff hist −4 m NES 2.0 Mapper 547 →CHR Banking Operation: sixteen bits, not sixteen bytes
19 August 2019
- 21:1921:19, 19 August 2019 diff hist +32 Overscan →PAL: 11:8 (0.8% too narrow) isn't enough better than 7:5
13 August 2019
- 18:5818:58, 13 August 2019 diff hist +368 Talk:Four player adapters →Rackets & Rivals
- 18:5618:56, 13 August 2019 diff hist +24 m Four player adapters →Compatible games: add Rackets & Rivals per talk page
12 August 2019
- 17:1517:15, 12 August 2019 diff hist 0 APU →Frame Counter ($4017): frm_quarter was wrong too; frm_d is entirely suppressed in 5-step mode.
- 17:1317:13, 12 August 2019 diff hist 0 APU →Frame Counter ($4017): mode 1 frm_half timing was wrong
10 August 2019
- 17:2217:22, 10 August 2019 diff hist −14 List of mappers by Release Date →Japan: header. a few better board names. remove second m140 game
2 August 2019
- 07:1107:11, 2 August 2019 diff hist 0 Taito TC0690 pinout arrows current
- 00:3000:30, 2 August 2019 diff hist +24 INES Mapper 048 link to pinout
- 00:2300:23, 2 August 2019 diff hist +2,056 N Taito TC0690 pinout Created page with "Category:PinoutsTaito TC0690: 64-pin 1.0mm pitch QFP (Canonically iNES Mapper 048) _____ n/c -- /01 64\ -- n/c..."
- 00:0900:09, 2 August 2019 diff hist +32 Hardware pinout →MMC: redlink to hold TC0690 pinout
24 July 2019
- 16:5816:58, 24 July 2019 diff hist +75 Errata the phrasing "disables and enables [...] while the bit is set" insinuates that this can only happen during one singular vblank. But it can happen at any length of time after NMIs have been disabled.
22 July 2019
- 18:4518:45, 22 July 2019 diff hist +352 CPU power up state →After reset: APU Frame Counter behavior differs between 2A03letterless and 2A03G
21 July 2019
- 23:2723:27, 21 July 2019 diff hist +53 CPU power up state →After reset: behavior of register behind writes to $4011 on reset is known
- 23:2523:25, 21 July 2019 diff hist +72 CPU power up state →At power-up: citation for $4010-4013 on-powerup state
15 July 2019
- 21:2521:25, 15 July 2019 diff hist −106 Mask ROM pinout →Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin): remove redundant "PRG" label on every pin, since it's stated in the lede, so that we can avoid labeling the pin "PRG /CE"
- 21:2021:20, 15 July 2019 diff hist 0 NROM-368 →Hardware: we almost exclusively call the signal on the card edge "/ROMSEL", not "PRG /CE". Replace the latter with the former for consistency. current
- 21:2021:20, 15 July 2019 diff hist 0 m 74139 →Signal descriptions: we almost exclusively call the signal on the card edge "/ROMSEL", not "PRG /CE". Replace the latter with the former for consistency. current
- 20:5420:54, 15 July 2019 diff hist 0 PRG RAM circuit we almost exclusively call the signal on the card edge "/ROMSEL", not "PRG /CE". Replace the latter with the former for consistency.
12 July 2019
- 17:3917:39, 12 July 2019 diff hist 0 VRC2 pinout add name for pin 18
- 17:2917:29, 12 July 2019 diff hist +211 VRC2 and VRC4 →Registers: add extsel, change address for layout cfg
- 01:5101:51, 12 July 2019 diff hist −172 UNROM 512 →InfiniteNESLives 4-screen board: a little less verbose
10 July 2019
- 21:3121:31, 10 July 2019 diff hist +110 User:Lidnariq/MMC3 Variants →ASIC mappers with simple banking: split out m195
- 21:2721:27, 10 July 2019 diff hist −172 INES Mapper 194 m195 isn't the same as m194, but instead more versatile current
9 July 2019
- 21:4021:40, 9 July 2019 diff hist +100 NES 2.0 Mapper 544 →CHR-RAM Bank Selection: CHR A18 exists, but is not connected to PAL, so so the same CHR RAM can be accessed via (at least) two different VRC4 banks
8 July 2019
- 21:1121:11, 8 July 2019 diff hist −54 UNROM 512 →RetroUSB board: mask means something, not what used to be here
3 July 2019
- 19:0719:07, 3 July 2019 diff hist +28 NES 2.0 Mapper 544 →CHR-RAM Bank Selection: VRC4 has 9 bit banks, call out that the MSbit both exists and is ignored
2 July 2019
- 19:2719:27, 2 July 2019 diff hist 0 VRC2 pinout explicitly call out OR gate inside VRC2/4
1 July 2019
- 18:4518:45, 1 July 2019 diff hist −1 m INES Mapper 195 edito
