User contributions for Lidnariq
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1 January 2019
- 02:1002:10, 1 January 2019 diff hist +1,176 Vs. System Make the introduction actually useful. Mention that it's not consistent whether a given physical control maps to $4016 or $4017.
- 01:4101:41, 1 January 2019 diff hist +3 Vs. System I should be consistent with my terminology. I already started using primary/secondary, so use that throughout.
- 01:4001:40, 1 January 2019 diff hist +507 Vs. System explain synchronization
31 December 2018
- 02:5802:58, 31 December 2018 diff hist −4 m MMC5 →8x16 mode enable 2 ($2001): edit-o
- 02:1602:16, 31 December 2018 diff hist +1 m MMC5 →CHR Bankswitching ($5120-$5130): braino
- 02:1502:15, 31 December 2018 diff hist +70 MMC5 →CHR Bankswitching ($5120-$5130): backref
- 02:1302:13, 31 December 2018 diff hist +6 m MMC5 →8x16 mode enable 2 ($2001): forgot to close cite
- 02:1302:13, 31 December 2018 diff hist +739 MMC5 →Configuration: Technically these registers are part of the MMC5
30 December 2018
- 23:1423:14, 30 December 2018 diff hist −4 m Emulators Reverted edits by Piotr Grochowski (talk) to last revision by Lidnariq
29 December 2018
- 22:3022:30, 29 December 2018 diff hist −4 Emulators Undo revision 15980 by Piotr Grochowski (talk) — like it or not, the official name and typography for Mac OS X is "macOS" now.
24 December 2018
- 20:1820:18, 24 December 2018 diff hist +438 MMC1 →Control (internal, $8000-$9FFF): mention power-on state gotchas.
22 December 2018
- 19:0519:05, 22 December 2018 diff hist −36 m MMC5 →CHR select $5120-$512B: Both "LSBit from register ignored" and "upper bits from register ignored" behaviors exist. Only VRC6, Mapper 90, MMC1, and MMC5 can select multiple different banking layouts. VRC6 PRG, m90 PRG & CHR, MMC5 CHR ignore MSbit.
21 December 2018
- 22:4422:44, 21 December 2018 diff hist +148 MMC5 →Emulation quicks with commercial games: typo. Explain what "Uncharted Waters" actually needs, because "PRG-RAM banking" is underspecified.
- 22:3922:39, 21 December 2018 diff hist −2 MMC5 →PRG-RAM bankswitching quircks: typoes
- 22:3822:38, 21 December 2018 diff hist −25 m MMC5 →PRG Bankswitching ($5113-$5117): grammar, typos, fluidity
- 22:3722:37, 21 December 2018 diff hist −65 MMC5 →PRG Bankswitching ($5113-$5117): VRC6's two PRG bankswitching registers specify offset as multiples of 16 KiB and 8 KiB. So remove false generalization.
15 December 2018
- 21:1821:18, 15 December 2018 diff hist +182 PPU registers →Bit 0 bus conflict: it's not a bus conflict, and we appear to have an accurate explanation of what's causing it now.
10 December 2018
- 20:3820:38, 10 December 2018 diff hist +1 Game bugs →Reliance on RAM values: break out comment about RAM as RNG seed to emphasize it
6 December 2018
- 05:5305:53, 6 December 2018 diff hist −96 m MMC5 pinout The SL3/CL3 solder jumpers aren't particularly close to #s 4-6 even on ELROM, and Ben Boldt has discovered pins 97/98 are unrelated anyway
4 December 2018
- 19:1919:19, 4 December 2018 diff hist −15 m Jissen Mahjong controller Swap out dead links for the archived copies. glad i had the foresight to snapshot the pages when i made this page.
26 November 2018
- 20:2920:29, 26 November 2018 diff hist +220 Talk:MMC5 →PRG Bankswitching
25 November 2018
- 20:2620:26, 25 November 2018 diff hist 0 MMC5 →PRG Bankswitching: use rowspan to unify places where the two address buses are the same in order to emphasize where the two buses differ
20 November 2018
- 07:5807:58, 20 November 2018 diff hist +463 Cycle reference chart →CPU cycle counts
- 03:2303:23, 20 November 2018 diff hist +474 Clock rate incorporate CPU cycles as extra derived information in this table
19 November 2018
- 19:1619:16, 19 November 2018 diff hist +90 CPU variants add T1818P
- 19:1419:14, 19 November 2018 diff hist +90 PPU variants add T1818P
3 November 2018
- 06:1506:15, 3 November 2018 diff hist −118 m Talk:Programming with unofficial opcodes Reverted edits by 208.71.141.54 (talk) to last revision by Pubby
1 November 2018
- 05:4605:46, 1 November 2018 diff hist +147 m TxROM →Board Types: mention TLBROM
7 October 2018
- 20:3820:38, 7 October 2018 diff hist −17 m INES Mapper 210 →PRG Select 2 / CHR-RAM Enable ($E800-$EFFF) w: fix copypasta
6 October 2018
- 20:4920:49, 6 October 2018 diff hist 0 m MMC5 pinout oops missed these
- 20:4820:48, 6 October 2018 diff hist +85 MMC5 pinout fixup arrows
5 October 2018
- 17:4217:42, 5 October 2018 diff hist +3 m Overscan typo
- 16:4616:46, 5 October 2018 diff hist +128 Talk:MMC3 pinout No edit summary
- 16:3916:39, 5 October 2018 diff hist +102 Talk:MMC5 pinout →Chip pinout rotated by 45°
2 October 2018
- 06:5406:54, 2 October 2018 diff hist +401 Talk:MMC1 →SXROM Heuristics
- 06:5006:50, 2 October 2018 diff hist +105 m Talk:MMC1 →SXROM Heuristics: add signature
30 September 2018
- 01:5301:53, 30 September 2018 diff hist +92 NES 2.0 Mapper 533 No edit summary current
- 01:5201:52, 30 September 2018 diff hist +120 NES 2.0 Mapper 533 a few more words about bus conflicts
- 01:1001:10, 30 September 2018 diff hist +4 CPU →Notes: I did the math wrong in my forum post, this is now corrected
27 September 2018
- 19:4419:44, 27 September 2018 diff hist −9 NES 2.0 Mapper 328 →Random number generator or Protection ($CE80-$CEFF, $FE80-$FEFF, read): it's copy protection, we don't need to muse on that. also i disassembled the relevant program. current
- 04:4804:48, 27 September 2018 diff hist −754 UNIF/FARID UNROM 8-IN-1 replace redundant page with redirect current
- 04:4604:46, 27 September 2018 diff hist −771 UNIF/FARID SLROM 8-IN-1 redirect to nes2 mapper number current
- 04:4604:46, 27 September 2018 diff hist +73 NES 2.0 Mapper 323 merge contents of UNIF MAPR page here. current
25 September 2018
- 20:2720:27, 25 September 2018 diff hist 0 m Bandai FCG board elide link to redirect to self
- 19:2519:25, 25 September 2018 diff hist +54 m INES Mapper 016 add links to pinouts here
- 19:2219:22, 25 September 2018 diff hist +20 m Bandai LZ93D50 pinout add cat
- 19:2019:20, 25 September 2018 diff hist +20 m Bandai FCG pinout add cat current
- 19:1819:18, 25 September 2018 diff hist +11 m Bandai FCG pinout the IC is a "FCG-1" so get that extra word out of the middle
- 07:2207:22, 25 September 2018 diff hist +190 GTROM →Hardware Teardown: better hardware description
18 September 2018
- 20:0520:05, 18 September 2018 diff hist +390 PPU palettes →2C03 and 2C05: mention monochrome bit behavior
