User contributions for Lidnariq
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20 December 2015
- 23:2523:25, 20 December 2015 diff hist +116 User:Lidnariq/MMC3 Variants →Mappers with outer banks: add UNIF/COOLBOY
- 00:1300:13, 20 December 2015 diff hist 0 m INES Mapper 012 capitalize ROM, fix indefinite antecedent, italicize game name
16 December 2015
- 20:3520:35, 16 December 2015 diff hist +139 INES Mapper 012 add link to retrofit, now that it's been tested
14 December 2015
- 22:0222:02, 14 December 2015 diff hist +141 Zapper →Output ($4016/$4017 read): explicitly state the nature of the trigger debouncing
8 December 2015
- 21:5721:57, 8 December 2015 diff hist +82 PPU palettes →2C04: include what these two colors are duplicates of
7 December 2015
- 22:3322:33, 7 December 2015 diff hist −71 m Talk:Action 53 Reverted edits by 176.119.74.89 (talk) to last revision by Zzo38
6 December 2015
- 21:4621:46, 6 December 2015 diff hist +97 INES Mapper 012 mapper port location
- 21:2521:25, 6 December 2015 diff hist 0 m INES Mapper 012 fix copypasta
26 November 2015
- 08:5908:59, 26 November 2015 diff hist 0 m UNIF/COOLBOY →Register interpretation: reorder controls to match order of descending address lines
25 November 2015
- 00:0800:08, 25 November 2015 diff hist −42 UNIF/COOLBOY →$6003: denser inline explanation of GNROM mode
24 November 2015
- 21:3921:39, 24 November 2015 diff hist +217 UNIF/COOLBOY →$6003: explicitly state mux behavior of GNROM mode here too
- 20:1020:10, 24 November 2015 diff hist +99 m UNIF/COOLBOY add cats, mmc3 link
- 08:1208:12, 24 November 2015 diff hist −41 UNIF/COOLBOY forgot to remove the bit about MMC3 PRG RAM permission in the lede.
- 07:2207:22, 24 November 2015 diff hist −103 UNIF/COOLBOY Oops, registers NOT gated on MMC3 PRG RAM protection.
- 02:4002:40, 24 November 2015 diff hist +41 UNIF/COOLBOY →Banking mode = $10: Explicitly mention PPU A12..A10 passthrough in GNROM mode
- 01:5801:58, 24 November 2015 diff hist −11 m UNIF/COOLBOY →$6003: make less indirect
- 01:5101:51, 24 November 2015 diff hist +517 UNIF/COOLBOY →Register interpretation: rewrite ... hopefully clearer. might be too hardware-centric...
- 01:2901:29, 24 November 2015 diff hist −110 UNIF/COOLBOY →Banking mode = $50: Don't explicitly mention CHR A17 weirdness, that should be handled by combining details of the other modes.
- 01:2401:24, 24 November 2015 diff hist +6 m UNIF/COOLBOY →Banking mode = $40: grammar
- 01:0901:09, 24 November 2015 diff hist +175 UNIF/COOLBOY →Registers: explicitly name IC connections
23 November 2015
- 23:4123:41, 23 November 2015 diff hist +3 UNIF/COOLBOY →$6001: clarity
- 23:3823:38, 23 November 2015 diff hist +3,278 N UNIF/COOLBOY Translated from FCEUX's source. Proofreading requested!
18 November 2015
- 23:0223:02, 18 November 2015 diff hist +56 Clock rate mention 2C07 clipping here too. We should link to this page more, or merge it in somewhere else
15 November 2015
- 21:5221:52, 15 November 2015 diff hist +13 INES Mapper 186 No edit summary
- 21:5121:51, 15 November 2015 diff hist +9 INES Mapper 186 No edit summary
- 21:4521:45, 15 November 2015 diff hist +52 INES Mapper 186 add caveat programmer
- 21:4521:45, 15 November 2015 diff hist 0 m INES Mapper 186 fix braino
- 21:4321:43, 15 November 2015 diff hist +969 INES Mapper 186 incorporate information from various sources.
8 November 2015
- 03:5003:50, 8 November 2015 diff hist +280 Errata →Video: mention the ability to trigger multiple NMIs per vblank
- 01:3101:31, 8 November 2015 diff hist −39 User:Lidnariq/MMC3 Variants Rephrase "8KiB RAM only" as "unbanked" so-as to not exclude the possibility of games uses CHR-ROM on these mappers
7 November 2015
- 19:5219:52, 7 November 2015 diff hist +83 INES Mapper 196 Grammar rewrite
30 October 2015
- 18:4318:43, 30 October 2015 diff hist +8 m Errata →Video: typo
29 October 2015
- 18:4418:44, 29 October 2015 diff hist +179 Talk:Hardware bugs and quirks No edit summary
24 October 2015
- 03:2803:28, 24 October 2015 diff hist −57 NINA-001 →Variants: The problem with the BNROM - NINA-001 conflation were the 3rd party boards that were HKO BNROMs with PRG-RAM, so don't exclude that. Also try to avoid implying that BNROM always has CHR RAM and NINA-001 always CHR ROM.
18 October 2015
- 22:1222:12, 18 October 2015 diff hist +47 NINA-001 →Variants: reiterate NINA-001 vs BNROM heuristic
14 October 2015
- 21:0621:06, 14 October 2015 diff hist +275 N User talk:NovaSquirrel/Nova-7 →CHR banking: new section
12 October 2015
- 20:5120:51, 12 October 2015 diff hist 0 NTSC video →Color Phases: h/t HardWareMan
11 October 2015
- 18:2218:22, 11 October 2015 diff hist +36 INES Mapper 193 No edit summary
- 18:1718:17, 11 October 2015 diff hist +114 m Talk:INES Mapper 193 No edit summary current
6 October 2015
- 00:3900:39, 6 October 2015 diff hist +220 Talk:CPU power up state →Consistent RAM power-up state?
26 September 2015
- 06:3106:31, 26 September 2015 diff hist −279 NES Game Genie IC pinout Add direction arrows, rename PRG/CHR→CPU/PPU, reformat, link to forum thread
25 September 2015
- 02:0202:02, 25 September 2015 diff hist +78 INES Mapper 037 mention purpose of the last NAND gate
24 September 2015
- 07:0307:03, 24 September 2015 diff hist +54 MMC1 pinout it's more correct to say that SEROM &c simply don't support banking, revise accordingly. Additionally, revise to be presented more like other ASIC pinouts on this wiki
23 September 2015
- 00:5600:56, 23 September 2015 diff hist +13 m MMC3 Fine, "deliberate" instead of "explicit". It's very much a conscious choice that has been made.
22 September 2015
- 20:5020:50, 22 September 2015 diff hist −93 MMC3 →Variants: Not clear what the comment about Gauntlet was doing here, but it definitely didn't belong in the middle of the description of Namco's 108.
- 20:4720:47, 22 September 2015 diff hist +107 MMC3 →Registers: More explicitly call out MMC6 differences; also refine comment about oversize PRG support
- 03:2403:24, 22 September 2015 diff hist +214 PPU palettes →2C04: mention 2C04 PPUMASK "gray"scale mode weirdness
20 September 2015
- 19:3719:37, 20 September 2015 diff hist +43 m VRC2 pinout consistency, use webarchive for romlab link
- 19:3419:34, 20 September 2015 diff hist 0 VRC2 pinout how did I not notice the absence of mirroring control?
14 September 2015
- 23:5023:50, 14 September 2015 diff hist +4 m User:Lidnariq/Microchip-style PPU documentation →REGISTER: PPUMASK: PPU rendering modifications: braino current
