INES Mapper 168

iNES Mapper 168 represents the board used for Racermate Challenge 2. It could be thought of as a hybrid of UNROM and CPROM.

Overview

• PRG ROM size: 64 KiB
• PRG ROM bank size: 16 KiB
• PRG RAM: No
• CHR capacity: 64 KiB RAM, half (or all) battery-backed.
• CHR bank size: 4 KiB
• Nametable mirroring: Hardwired vertical mirroring
• Subject to bus conflicts: no

Banks

• CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
• CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
• PPU $0000-$0FFF: 4 KiB CHR RAM bank, fixed to the last bank, but see notes in Hardware.
• PPU $1000-$1FFF: 4 KiB switchable CHR RAM bank, two's complement of written value (write 7 = bank 8)

Jumpers

• J1: force deselect SRAM U1 when +5V fails
• J2: allow SRAM U1 to remain selected after +5V fails
• J3: Power SRAM U1 from +5V line
• J4: Power SRAM U1 from battery-backed supply

SRAM U2 is always protected and battery-backed.

J1+J4 vs J2+J3 should be selected as a pair. This modification allows 64kB of battery-backed memory.

Registers

Bank Select ($8000-$BFFF)

7  bit  0
---- ----
PPxx CCCC
||   ||||
||   ++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
++-------- Select 4 KB CHR RAM bank for PPU $1000-$1FFF

RAM Protection ($C000-$FFFF)

15   11 address   0  7 data  0
---- ---- ---- ----  ---- ----
11.. .... X... ....  XXXX XXXX
          |          |||| ||||
          +----------++++-++++- Write 1 then 0 to deprotect SRAM

Only one of the 9 above bits is used, but the software has no a priori reason to know which. The firmware thus writes $FF to $F080 and $00 to $F000.

Interrupt

Depending on which position for R2 is populated, the /IRQ line will be driven low with a 50% duty cycle for a period of either 2048 or 4096 M2 cycles. (874 or 437 Hz)

Hardware

This cartridge uses two 74LS00s, two 74HCT32s, a 74HCT74, a 74HCT4040, and a PNP transistor as a low-voltage detection circuit.

Unlike CPROM or iNES Mapper 180, which use AND logic to fix the first bank to 0 and switch the upper bank, the CHR-RAM here instead uses NAND logic. Because nothing else can read or write the RAMs except through this interface, the only question is whether the fixed bank is battery backed. It is NOT.

It is of casual interest, but also completely irrelevant, that the lower bits of the CHR bank register are out of order: 3012. Once again, because nothing else can read or write the RAMs except through this bank register, this only could matter if one were to desolder the RAMs to read them.

The hardware also seems to automatically de-protect CHR RAM because the 2⁵s bit of the 74HCT4040 U10 is connected to the /PRESET input of the 74HCT74 U9, so writes to the RAM Protection register seem redundant.

There is a space on the PCB to accept a donor CIC, labelled U11.

The RAM protection circuit on the PCB clearly originally used CPU A7, however the one pictured in NesCartDB has been modified to use CPU D2 instead.