INES Mapper 137

iNES Mapper 137 is used to represent the Sachen 8259D board. It is similar to the Sachen 8259A-C boards, but has some important differences. The information here comes primarily from FCEU-mm and may have some inaccuracies.

Overview

• PRG ROM size: up to 128 KiB
• PRG ROM bank size: 32 KiB
• PRG RAM: No
• CHR capacity: up to 32KiB ROM
• CHR bank size: 1 KiB / 4KiB
• Nametable mirroring: Mapper controlled
• Subject to bus conflicts: No

Variants

There is only one known 8259D game, The Great Wall. It has 32KiB PRG ROM and 32KiB CHR ROM. It has been seen in the wild as iNES 137 and UNIF "UNL-Sachen-8259D".

Banks

• CPU $8000-$FFFF: 32KiB switchable PRG ROM bank
• PPU $0000-$03FF: 1KiB switchable CHR ROM bank
• PPU $0400-$07FF: 1KiB switchable CHR ROM bank
• PPU $0800-$0BFF: 1KiB switchable CHR ROM bank
• PPU $0C00-$0FFF: 1KiB switchable CHR ROM bank
• PPU $1000-$1FFF: fixed to last 4KiB of CHR ROM

Registers

Registers should be masked with $C101.

Reg Select ($4100)

7  bit  0
---- ----
.... .rrr
      |||
      +++- Select register number for next data write

Reg Data ($4000, $4001, $4101)

7  bit  0
---- ----
.... .ddd
      |||
      +++- Output data to register selected by $4100.

Chr Select (Internal 0-3)

7  bit  0
---- ----
.... .ccc
      |||
      +++- Select lower 3 bits of 1KiB CHR block for PPU $0000/$0400/$0800/$0C00

Chr Top Bits (Internal 4)

7  bit  0
---- ----
.... .DCB
      |||
      ||+- Select bit #4 for chr reg 1
      |+-- Select bit #4 for chr reg 2
      +--- Select bit #4 for chr reg 3

Prg Bank (Internal 5)

7  bit  0
---- ----
.... .ppp
      |||
      +++- Select 32KiB PRG bank for CPU $8000

Chr 3 Bit #3 (Internal 6)

7  bit  0
---- ----
.... ...E
        |
        +- Select bit #3 for chr reg 3

Putting all of this together, the 4 chr regs have the following bit layouts:

7  bit  0
---- ----
...0 0ccc  chr reg 0
...B 0ccc  chr reg 1
...C 0ccc  chr reg 2
...D Eccc  chr reg 3

So only chr reg 3 can access all possible locations in CHR ROM.

Mode and Mirroring Select (Internal 7)

7  bit  0
---- ----
.... .mms
      |||
      ||+- Enable "simple" mode. (mirroring is fixed to V, and ignoring registers 1-3)
      ++-- Select mirroring (0 = V, 1 = H, 2 = (0,1,1,1), 3 = 1scA)

Caution: the above is suspect. The only game only writes 0x2 to this register (i.e. mm=1) and wants vertical mirroring/horizontal layout. Additionally, some rewiring is necessary for the reduced bank size, and so there are two likely behaviors:

1. Select mirroring (0,1,2=V; 3=1scA), and
2. Select mirroring (0=H, 1=V, 2=L, 3=1scA)