Jaleco SS 88006 pinout

Jaleco SS 88006: 42-pin 0.6" shrink DIP (Canonically mapper 18)

                  SS 88006
                 .---\/---.
       (f) M2 -> |01    42| -- VCC
(frw) CPU A12 -> |02    41| -> PRG RAM +CE (w)
  (f) CPU A13 -> |03    40| -> PRG RAM /CE (w) (Also shorted to RAM /OE)
  (f) CPU A14 -> |04    39| -> PRG RAM /WE (w)
  (r) PRG /CE <- |05    38| -> µPD775x /RESET
  (r) PRG A15 <- |06    37| -> µPD775x /START
  (r) PRG A14 <- |07    36| -> CIRAM A10 (f)
  (r) PRG A13 <- |08    35| <- PPU /RD (fr)
  (r) PRG A16 <- |09    34| ?? ?
  (r) PRG A17 <- |10    33| -> CHR A10 (r)
  (r) PRG A18 <- |11    32| -> CHR A16 (r)
 (frw) CPU A1 -> |12    31| -> CHR A11 (r)
 (frw) CPU A0 -> |13    30| -> CHR A13 (r)
 (frw) CPU D0 -> |14    29| -> CHR A12 (r)
 (frw) CPU D1 -> |15    28| -> CHR A14 (r)
 (frw) CPU D2 -> |16    27| -> CHR A15 (r)
 (frw) CPU D3 -> |17    26| ?? ?
      (f) R/W -> |18    25| <- PPU A13 (fr)
  (f) /ROMSEL -> |19    24| <- PPU A12 (f)
     (f) /IRQ <- |20    23| <- PPU A11 (f)
          GND -- |21    22| <- PPU A10 (f)
                 '--------'

Some PCBs include an external 7432 to delay M2 and/or /ROMSEL.

The associated ADPCM IC is wired as:

           µPD7755/6C
             __  __
(I4) PRG D6 |01\/18| PRG D5 (I3)
(I5) PRG D7 |02  17| PRG D4 (I2)
   (I6) GND |03  16| PRG D3 (I1)
   (I7) GND |04  15| PRG D2 (I0)
(volume) R2 |05  14| /START
  sound out |06  13| GND (/CS)
     (BUSY) |07  12| X1
     /RESET |08  11| X2
        GND |09  10| VCC
            '------'

Source: [1]