CPU Test Mode
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2A03E ???
The schematic for the Playchoice 10 permits the supervisor CPU to stop or "res" the 2A03E; the signal is synchronized to M2 before it gets into the 2A03E. Testing with just a button only crashed the 2A03E, so the synchronization must be necessary.
2A03G / 2A03H Test Mode
Pin 30 of the 2A03 revision G can be activated to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:
R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume)
and T=triangle (anywhere from 0 to 15)
R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel (same as value written to $4011)
W$401A: [L..T TTTT] - set state of triangle's sequencer to T, and lock all channels
(pulse+noise always output current volume, triangle/DPCM no longer advance) if L=1
2A03letterless Programmable Interval Timer
Visual inspection of the original 2A03 revision indicates there was planned IRQ functionality from $401C-$401F, but this was left unfinished and unusable and was outright removed from later CPU revisions.
W$401C,D,E: write lower, middle, upper bits of counter reload value
R$401C,D,E: read lower, middle, upper bits of current counter value
W$401F: [ELAC DTZC]
|||| ||||
|||+----+-- Clock source
||| ||| 00: M2÷16 10: M2÷256
||| ||| 01: Rising edges of JOY2 11: Falling edges of JOY2
||| ||+--- Exists but does nothing. Toggles (invisibly) on terminal count.
||| |+---- Value driven out on JOY1. Toggles on terminal count.
||| +----- 1:count up; 0:count down
||+-------- 1:automatic reload when counter reaches 0; 0:counter stops while zero
|+--------- 1:reload immediately
+---------- 1:IRQ enabled (counts regardless)
R$401F: [E... ...I]
| |
| +-- Timer IRQ would be asserted if enabled
+---------- IRQ is enabled
Reads from $401F acknowledge the IRQ
