TXC 05-00002-010 pinout
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05-00002-010: 24-pin 0.3" DIP. (Mappers 036, 132, and 173)
.--\/--. Q2 <- |01 24| -> Q3 Q1 <- |02 23| -> Q4 Q0 <- |03 22| -> o3 i1 -> |04 21| <- CPU A13 (rn) i0 -> |05 20| <- CPU A14 (rn) io2 <> |06 19| -- GND 5V -- |07 18| <- CPU R/W (n) D5 <> |08 17| <- /ROMSEL (rn) D4 <> |09 16| <- M2 (n) D2 <> |10 15| <- CPU A8 (rn) D1 <> |11 14| <- CPU A1 (rn) D0 <> |12 13| <- CPU A0 (rn) '------'
There is a lot more functionality here than was used in any of the three mappers that used it.
On mapper 36, this ASIC is connected as:
.--\/--. NC <- |01 24| -> NC (r) PRG A16 <- |02 23| -> NC (r) PRG A15 <- |03 22| -> NC GND -> |04 21| <- CPU A13 (rn) 5V -> |05 20| <- CPU A14 (rn) NC <> |06 19| -- GND 5V -- |07 18| <- CPU R/W (n) NC <> |08 17| <- /ROMSEL (rn) NC <> |09 16| <- M2 (n) NC <> |10 15| <- CPU A8 (rn) (rn) CPU D5 <> |11 14| <- CPU A1 (rn) (rn) CPU D4 <> |12 13| <- CPU A0 (rn) '------'
On mapper 132:
.--\/--. (r) PRG A15 <- |01 24| -> NC (r) CHR A14 <- |02 23| -> NC (r) CHR A13 <- |03 22| -> NC GND -> |04 21| <- CPU A13 (fr) 5V -> |05 20| <- CPU A14 (fr) NC <> |06 19| -- GND 5V -- |07 18| <- CPU R/W (f) GND <> |08 17| <- /ROMSEL (fr) (fr) CPU D3 <> |09 16| <- M2 (f) (fr) CPU D2 <> |10 15| <- CPU A8 (fr) (fr) CPU D1 <> |11 14| <- CPU A1 (fr) (fr) CPU D0 <> |12 13| <- CPU A0 (fr) '------'
On mapper 173, labeled "ITC20V8-10LP"
.--\/--. NC <- |01 24| -> NC (r) CHR A15 <- |02 23| -> NC (r) CHR A13 <- |03 22| -> CHR A14 GND -> |04 21| <- CPU A13 (fr) 5V -> |05 20| <- CPU A14 (fr) NC <> |06 19| <- GND 5V -- |07 18| <- CPU R/W (f) GND <> |08 17| <- /ROMSEL (fr) (fr) CPU D3 <> |09 16| <- M2 (f) (fr) CPU D2 <> |10 15| <- CPU A8 (fr) (fr) CPU D1 <> |11 14| <- CPU A1 (fr) (fr) CPU D0 <> |12 13| <- CPU A0 (fr) '------'