Sunsoft FME-7
The Sunsoft FME-7 represents two mapper ICs which work identically, except that one contains extra sound hardware. The FME-7 is the base memory mapper with no additional sound hardware. The Sunsoft 5B is an FME-7 with the addition of extra sound hardware. Both the Sunsoft 5B and FME-7 exist as a 44 pin TQFP. It is emulated as iNES Mapper 069.
In Europe, boards using the FME-7 were labeled as JSROM and JLROM. The FME-7 mapper was used in only one game released in the US, Batman: Return of the Joker.
Overview
- Manufacturer: Sunsoft
- PRG ROM Size: Up to 256 KiB (possibly up to 512 KiB)
- PRG ROM Bank Size: 8 KiB
- PRG RAM: Up to 8 KiB (512 KiB likely supported)
- CHR capacity: 256 KiB
- CHR Bank Size: 1 KiB
- Nametable mirroring: Controlled by Mapper: H, V, 1scA, 1scB
- Subject to bus conflicts: No
Banks
- CPU $6000-$7FFF: 8 KB Bankable PRG ROM or PRG RAM
- CPU $8000-$9FFF: 8 KB Bankable PRG ROM
- CPU $A000-$BFFF: 8 KB Bankable PRG ROM
- CPU $C000-$DFFF: 8 KB Bankable PRG ROM
- CPU $E000-$FFFF: 8 KB PRG ROM, fixed to the last bank of ROM
- PPU $0000-$03FF: 1 KB Bankable CHR ROM
- PPU $0400-$07FF: 1 KB Bankable CHR ROM
- PPU $0800-$0BFF: 1 KB Bankable CHR ROM
- PPU $0C00-$0FFF: 1 KB Bankable CHR ROM
- PPU $1000-$13FF: 1 KB Bankable CHR ROM
- PPU $1400-$17FF: 1 KB Bankable CHR ROM
- PPU $1800-$1BFF: 1 KB Bankable CHR ROM
- PPU $1C00-$1FFF: 1 KB Bankable CHR ROM
Registers
Configuration of the FME-7 is accomplished by first writing the command number to the Command Register, then writing the command's parameter byte to the Parameter Register.
Command Register ($8000)
7 bit 0 ---- ---- .... CCCC |||| ++++- The command number to invoke when writing to the Parameter Register
Parameter Register ($A000)
7 bit 0 ---- ---- PPPP PPPP |||| |||| ++++-++++- The parameter to use for this command. Writing to this register invokes the command in the Command Register.
Commands
In order to invoke a command first write the command's number to the Command Register, then the desired parameter to the Parameter Register.
CHR Bank 0 ($0)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0000 - $03FF
CHR Bank 1 ($1)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0400 - $07FF
CHR Bank 2 ($2)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0800 - $0BFF
CHR Bank 3 ($3)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0C00 - $0FFF
CHR Bank 4 ($4)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1000 - $13FF
CHR Bank 5 ($5)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1400 - $17FF
CHR Bank 6 ($6)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1800 - $1BFF
CHR Bank 7 ($7)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1C00 - $1FFF
PRG Bank 0 ($8)
7 bit 0 ---- ---- ERBB BBBB |||| |||| ||++-++++- The bank number to select at CPU $6000 - $7FFF |+------- RAM / ROM Select Bit | 0 = PRG ROM | 1 = PRG RAM +-------- RAM Enable Bit (6264 +CE line) 0 = PRG RAM Disabled 1 = PRG RAM Enabled
It is very likely that a cartridge could be modified to support banking up to 512KiB of PRG-RAM here. However, no game was ever released with more than 8KiB and this is currently untested.
If the RAM / ROM Select Bit is 1 (RAM selected), but the RAM Enable Bit is 0 (disabled) the data bus will be open. This is a limited form of WRAM write protection on power-up.
There is a tentative report that not all games honor some or any of the bits in this register. Corroboration is needed before any action is taken.
PRG Bank 1 ($9)
7 bit 0 ---- ---- ..BB BBBB || |||| ++-++++- The bank number to select at CPU $8000 - $9FFF
PRG Bank 2 ($A)
7 bit 0 ---- ---- ..BB BBBB || |||| ++-++++- The bank number to select at CPU $A000 - $BFFF
PRG Bank 3 ($B)
7 bit 0 ---- ---- ..BB BBBB || |||| ++-++++- The bank number to select at CPU $C000 - $DFFF
Name Table Mirroring ($C)
7 bit 0 ---- ---- .... ..MM || ++- Mirroring Mode 0 = Vertical 1 = Horizontal 2 = One Screen Mirroring from $2000 ("1ScA") 3 = One Screen Mirroring from $2400 ("1ScB")
IRQ Control ($D)
7 bit 0 ---- ---- C... ...T | | | +- IRQ Enable | 0 = Do not generate IRQs | 1 = Do generate IRQs +-------- IRQ Counter Enable 0 = Disable Counter Decrement 1 = Enable Counter Decrement
IRQ Counter Low Byte ($E)
7 bit 0 ---- ---- LLLL LLLL |||| |||| ++++-++++- The low eight bits of the IRQ counter. Note that setting this register directly sets the lower eight bits of the counter.
IRQ Counter High Byte ($F)
7 bit 0 ---- ---- HHHH HHHH |||| |||| ++++-++++- The high eight bits of the IRQ counter. Note that setting this register directly sets the upper eight bits of the counter.
IRQ Operation
The IRQ feature of FME-7 is a CPU cycle counting IRQ generator. When enabled the 16-bit IRQ counter is decremented once per CPU cycle. When the IRQ counter is decremented from $0000 to $FFFF an IRQ is generated. The IRQ line is held low until it is acknowledged.
How to Use the IRQ Generator
- Set the counter to the desired number of cycles minus one.
- Enable the IRQ generator by turning on both the IRQ Enable and IRQ Counter Enable flags of the IRQ Control command.
- Within the IRQ handler, turn off the IRQ Enable flag of the IRQ Control command.
- This acknowledges the IRQ.
- Optional: Go back to Step 1 for the next IRQ.