NTDEC TC-112 pinout: Difference between revisions
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(update pins 21, 23, 24) |
m (argh) |
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(n) PPU A13 -> |15 26| -> CHR2 /CE (r) | (n) PPU A13 -> |15 26| -> CHR2 /CE (r) | ||
(n) PPU A12 -> |16 25| <- CPU D0 (nr) | (n) PPU A12 -> |16 25| <- CPU D0 (nr) | ||
(n) PPU A11 -> |17 24| -> / | (n) PPU A11 -> |17 24| -> /W6005 | ||
(nr)PPU A10 -> |18 23| -> / | (nr)PPU A10 -> |18 23| -> /W6006 | ||
† PPU /RD -> |19 22| <- CPU A2 (nr) | † PPU /RD -> |19 22| <- CPU A2 (nr) | ||
GND -- |20 21| -> CIRAM A10 (n) | GND -- |20 21| -> CIRAM A10 (n) |
Revision as of 18:15, 6 February 2020
NTDEC TC-112: 40-pin 0.6" PDIP. (Canonically iNES Mapper 193)
.---\/---. (n) M2 -> |1 40| -- VCC (nr) CPU D7 -> |2 39| -> PRG A16 (r) (nr) CPU D6 -> |3 38| -> PRG A15 (r) (nr) CPU D5 -> |4 37| -> PRG A14 (r) (nr) CPU D4 -> |5 36| -> PRG A13 (r) (nr) CPU D3 -> |6 35| -> PRG1 /CE (r) (nr) CPU D2 -> |7 34| -> PRG2 /CE (r) (nr) CPU D1 -> |8 33| -> CHR A16 (r) (nr) CPU A1 -> |9 32| -> CHR A15 (r) (nr) CPU A0 -> |10 31| -> CHR A14 (r) (n) CPU R/W -> |11 30| -> CHR A13 (r) (n) CPU /CE -> |12 29| -> CHR A12 (r) (n) CPU A14 -> |13 28| -> CHR A11 (r) (n) CPU A13 -> |14 27| -> CHR1 /CE (r) (n) PPU A13 -> |15 26| -> CHR2 /CE (r) (n) PPU A12 -> |16 25| <- CPU D0 (nr) (n) PPU A11 -> |17 24| -> /W6005 (nr)PPU A10 -> |18 23| -> /W6006 † PPU /RD -> |19 22| <- CPU A2 (nr) GND -- |20 21| -> CIRAM A10 (n) `--------'
† On one board, connected to a seemingly-needlessly-complicated 7400 circuit. See the thread on the forum.
Sources: