NINA-001: Difference between revisions
(→Variants: The problem with the BNROM - NINA-001 conflation were the 3rd party boards that were HKO BNROMs with PRG-RAM, so don't exclude that. Also try to avoid implying that BNROM always has CHR RAM and NINA-001 always CHR ROM.) |
(→Hardware: explain mechanism of action, and mention trivial oversize support in hardware) |
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The NINA-001 board contains a 74LS133 (13-input NAND gate), 74LS74 (dual D flip-flop), 74HCT139 (dual 1-4 decoder), 74LS00 (quad 2-input NAND gate), two 74HCT173s (4-bit tristate D flip-flop), as well as a microcontroller labelled NINA to act as a [[CIC]] defeat mechanism. | The NINA-001 board contains a 74LS133 (13-input NAND gate), 74LS74 (dual D flip-flop), 74HCT139 (dual 1-4 decoder), 74LS00 (quad 2-input NAND gate), two 74HCT173s (4-bit tristate D flip-flop), as well as a microcontroller labelled NINA to act as a [[CIC]] defeat mechanism. | ||
These 4 registers reside "on top" of PRG RAM: each write to the register goes both to the register and to the RAM location at the same address. Thus, reading the register's address returns the last value written to the RAM, which is also the last value written to the register. | These 4 registers reside "on top" of PRG RAM: each write to the register goes both to the register and to the RAM location at the same address. Thus, reading the register's address returns the last value written to the RAM, which is also the last value written to the register. | ||
One 2-NAND and one half of the 74'139 together generate /RAMSEL. Another 2-NAND inverts that to form +RAMSEL. A third 2-NAND inverts R/W to produce +WR. The 13-NAND combines +RAMSEL, +WR, and A12…A2 to generate /REGSEL. The other half of the 74'139 uses /REGSEL, A1, and A0 to generate the latching signals for the three flip-flops. | |||
The final 2-NAND inverts PPU A12. PPU A12 and PPU /A12 are fed to the two 74'173s /OE inputs, implementing a simple quad 1-of-2 multiplexer. | |||
This hardware has a trivial oversize definition that supports 8 MiB PRG and 1 MiB CHR, made by replacing the three flip-flops with 74'374s. | |||
== Variants == | == Variants == | ||
Revision as of 23:42, 17 April 2016
NINA-001 is a particular third-party cartridge board used by American Video Entertainment. The iNES format assigns mapper 34 to this board (as well as BxROM).
Overview
- PRG ROM size: 64 KB
- PRG ROM bank size: 32 KB
- PRG RAM: 8 KB, not battery backed [1]
- CHR ROM capacity: 64 KB ROM
- CHR bank size: 4 KB
- Nametable mirroring: hardwired to horizontal mirroring
- Subject to bus conflicts: No
Banks
- CPU $8000-$FFFF: 32 KB switchable PRG ROM bank
- PPU $0000-$0FFF: 4 KB switchable CHR ROM bank
- PPU $1000-$1FFF: 4 KB switchable CHR ROM bank
Registers
PRG bank select ($7FFD)
7 bit 0
---- ----
xxxx xxxP
|
+- Select 32 KB PRG ROM bank for CPU $8000-$FFFF
CHR bank select 0 ($7FFE)
7 bit 0
---- ----
xxxx CCCC
||||
++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
CHR bank select 1 ($7FFF)
7 bit 0
---- ----
xxxx CCCC
||||
++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
Hardware
The NINA-001 board contains a 74LS133 (13-input NAND gate), 74LS74 (dual D flip-flop), 74HCT139 (dual 1-4 decoder), 74LS00 (quad 2-input NAND gate), two 74HCT173s (4-bit tristate D flip-flop), as well as a microcontroller labelled NINA to act as a CIC defeat mechanism. These 4 registers reside "on top" of PRG RAM: each write to the register goes both to the register and to the RAM location at the same address. Thus, reading the register's address returns the last value written to the RAM, which is also the last value written to the register.
One 2-NAND and one half of the 74'139 together generate /RAMSEL. Another 2-NAND inverts that to form +RAMSEL. A third 2-NAND inverts R/W to produce +WR. The 13-NAND combines +RAMSEL, +WR, and A12…A2 to generate /REGSEL. The other half of the 74'139 uses /REGSEL, A1, and A0 to generate the latching signals for the three flip-flops.
The final 2-NAND inverts PPU A12. PPU A12 and PPU /A12 are fed to the two 74'173s /OE inputs, implementing a simple quad 1-of-2 multiplexer.
This hardware has a trivial oversize definition that supports 8 MiB PRG and 1 MiB CHR, made by replacing the three flip-flops with 74'374s.
Variants
The iNES mapper used to implement this mapper also includes a writable register at $8000-$FFFF for emulation of the BxROM boardset which has caused many headaches for NES emulator authors. Emulator developers should consider switching between NINA-001 emulation and BxROM emulation based on the amount of CHR (≥ 16KiB implies NINA-001; ≤ 8KiB implies BNROM).
