NES 2.0 submappers: Difference between revisions

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(MMC1 and MMC3)
(per kevtris on IRC: VRC4 looks good, and he made but never released submapper specs for MMC1 and MMC3)
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== MMC1 ==
== MMC1 ==
Status: Draft
Most [[SxROM|MMC1 boards]] wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner.
Most [[SxROM|MMC1 boards]] wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner.
But among boards designed to take a 32 KiB PRG ROM, some (SIROM) connect PRG ROM A14 to the MMC1's output, others (SEROM, SHROM, SH1ROM) directly to CPU A14.
But among boards designed to take a 32 KiB PRG ROM, some (SIROM) connect PRG ROM A14 to the MMC1's output, others (SEROM, SHROM, SH1ROM) directly to CPU A14.
KH made a specification for MMC1 submappers in October 2006 but never released it.


== MMC3 ==
== MMC3 ==
Status: Draft
Status: Draft


No submapper of [[iNES Mapper 004|mapper 4]] is needed to distinguish [[MMC3]] from [[MMC6]], as any MMC6-sized PRG RAM will behave like MMC6.
No submapper of [[iNES Mapper 004|mapper 4]] is needed to distinguish [[MMC3]] from [[MMC6]], as any board with MMC6-sized PRG RAM will behave like MMC6.
But there are two general kinds of MMC3 IRQ: the old style, which disables the IRQ when the latch is loaded with 0, and the new style, which produces an IRQ on every scanline.
But there are two general kinds of MMC3 IRQ: the old style, which disables the IRQ when the latch is loaded with 0, and the new style, which produces an IRQ on every scanline.
Some newer games rely on the new style behavior.
Some newer games rely on the new style behavior.
KH made a specification for MMC3 submappers in October 2006 but never released it.


== [[iNES Mapper 078]] ==
== [[iNES Mapper 078]] ==
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== VRC4 ==
== VRC4 ==
Status: Draft
Konami's [[VRC4]] mapper has five known variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper.
Konami's [[VRC4]] mapper has five known variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper.
These are spread across three mappers: two for [[iNES Mapper 021|21]], two for [[iNES Mapper 025|25]], and one for [[iNES Mapper 023|23]].
These are spread across three mappers: two for [[iNES Mapper 021|21]], two for [[iNES Mapper 025|25]], and one for [[iNES Mapper 023|23]].

Revision as of 13:59, 24 September 2012

Submapper is a term used in the NES 2.0 header for 4-bit codes designating functionally distinct variants of iNES mappers that cannot be distinguished by the memory size fields alone. Most emulators using iNES format distinguish these using CRC, SHA-1, or other hashes of the PRG ROM and CHR ROM, but this works only for games published prior to 1997, and not for new games on the same mapper.

As of early 2012, no submappers were officially defined, but in mid-2012, a drive to collect proposals began. One proposed general principle for backward compatibility is that submapper 0 be reserved for the default iNES behavior.

MMC1

Most MMC1 boards wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner. But among boards designed to take a 32 KiB PRG ROM, some (SIROM) connect PRG ROM A14 to the MMC1's output, others (SEROM, SHROM, SH1ROM) directly to CPU A14.

KH made a specification for MMC1 submappers in October 2006 but never released it.

MMC3

Status: Draft

No submapper of mapper 4 is needed to distinguish MMC3 from MMC6, as any board with MMC6-sized PRG RAM will behave like MMC6. But there are two general kinds of MMC3 IRQ: the old style, which disables the IRQ when the latch is loaded with 0, and the new style, which produces an IRQ on every scanline. Some newer games rely on the new style behavior.

KH made a specification for MMC3 submappers in October 2006 but never released it.

iNES Mapper 078

Status: Draft

Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have it set up to switch between horizontal and vertical mirroring, where the bit controls a mux between PA10 and PA11 whose output is sent to CIRAM A10.

VRC4

Konami's VRC4 mapper has five known variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper. These are spread across three mappers: two for 21, two for 25, and one for 23. There are theoretically 8*7 = 56 ways to wire these, but in all five extant possibilities, two adjacent address lines are used: A2 and A1, A0 and A1, A7 and A6, A2 and A3, and A3 and A2. But all 14 possibilities easily fit in a submapper number:

3210
||||
|+++- Which address line corresponds is wired to the A1 in the VRC4a
+---- 0: Use next lower address line for VRC4a A2; 1: use next higher line

The values 0 (A0 and next lower) and 15 (A7 and next higher) are impossible.

The VRC4 article describes the ports by mapping them to the variant called "VRC4a" on that page, which uses A2 and A1, putting the four VRC IRQ ports (IRQ Latch low, IRQ Latch high, IRQ Control, and IRQ Acknowledge) at $F000, $F002, $F004, and $F006.

Nickname A2 A1 Registers iNES mapper NES 2.0 submapper
VRC4a A2 A1 $x000, $x002, $x004, $x006 21 9
VRC4b A0 A1 $x000, $x002, $x001, $x003 25 1
VRC4c A7 A6 $x000, $x040, $x080, $x0C0 21 14
VRC4d A2 A3 $x000, $x008, $x004, $x00C 25 3
VRC4e A3 A2 $x000, $x004, $x008, $x00C 23 10