MMC5

The Nintendo MMC5 is a mapper ASIC used in Nintendo's ExROM Game Pak boards. All MMC5 boards are assigned to iNES Mapper 005.

Overview

• PRG ROM size: Up to 1024 KB
• PRG ROM bank size: 8 KB, 16 KB, or 32 KB
• PRG RAM: Up to 64 KB
• CHR capacity: Up to 1024 KB ROM (RAM support unknown)
• CHR bank size: 1 KB, 2 KB, 4 KB, or 8 KB
• Nametable mirroring: Controlled by mapper
• Subject to bus conflicts: No

The MMC5 is the most powerful mapper ASIC Nintendo made for the NES and Famicom.

It supports many advanced features, including:

• 4 PRG ROM switching modes
• 4 CHR ROM switching modes
• Up to 64KB of WRAM, mappable not only at $6000-$7FFF but also within $8000-$DFFF
• An 8-bit multiplier for performing quick calculations
• A scanline based IRQ counter
• The ability to use different CHR banks for background and 8x16 sprites
• 1024 bytes of on-chip memory, which can be used for 4 different purposes:
  • An extra general-use nametable
  • Attribute and tile index expansion - address 16384 background tiles at once, and allow each individual 8x8 tile to have its own palette setting
  • Vertical split-screen
  • Extra RAM for storing program variables
• Three extra sound channels
  • Two pulse channels, identical to those in the NES APU (except lacking pitch sweeps).
  • An 8-bit RAW PCM channel
• A 'fill mode' nametable, which can be instantly set to contain a specific tile in a specific color (useful for quickly getting a blank screen of a particular color/pattern)

Banks

The MMC5 provides 4 distinct banking modes for both PRG ROM and CHR ROM.

PRG mode 0

• CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
• CPU $8000-$FFFF: 32 KB switchable PRG ROM bank

PRG mode 1

• CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
• CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
• CPU $C000-$FFFF: 16 KB switchable PRG ROM bank

PRG mode 2

• CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
• CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
• CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
• CPU $E000-$FFFF: 8 KB switchable PRG ROM bank

PRG mode 3

• CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
• CPU $8000-$9FFF: 8 KB switchable PRG ROM/RAM bank
• CPU $A000-$BFFF: 8 KB switchable PRG ROM/RAM bank
• CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
• CPU $E000-$FFFF: 8 KB switchable PRG ROM bank

CHR mode 0

• PPU $0000-$1FFF: 8 KB switchable CHR bank

CHR mode 1

• PPU $0000-$0FFF: 4 KB switchable CHR bank
• PPU $1000-$1FFF: 4 KB switchable CHR bank

CHR mode 2

• PPU $0000-$07FF: 2 KB switchable CHR bank
• PPU $0800-$0FFF: 2 KB switchable CHR bank
• PPU $1000-$17FF: 2 KB switchable CHR bank
• PPU $1800-$1FFF: 2 KB switchable CHR bank

CHR mode 3

• PPU $0000-$03FF: 1 KB switchable CHR bank
• PPU $0400-$07FF: 1 KB switchable CHR bank
• PPU $0800-$0BFF: 1 KB switchable CHR bank
• PPU $0C00-$0FFF: 1 KB switchable CHR bank
• PPU $1000-$13FF: 1 KB switchable CHR bank
• PPU $1400-$17FF: 1 KB switchable CHR bank
• PPU $1800-$1BFF: 1 KB switchable CHR bank
• PPU $1C00-$1FFF: 1 KB switchable CHR bank

Registers

Sound

For details on sound operation, see MMC5_audio

Configuration

PRG mode ($5100)

7  bit  0
---- ----
xxxx xxPP
       ||
       ++- Select PRG banking mode

• 0 - One 32KB bank
• 1 - Two 16KB banks
• 2 - One 16KB bank ($8000-$BFFF) and two 8KB banks ($C000-$DFFF and $E000-$FFFF)
• 3 - Four 8KB banks

CHR mode ($5101)

7  bit  0
---- ----
xxxx xxCC
       ||
       ++- Select CHR banking mode

• 0 - 8KB CHR pages
• 1 - 4KB CHR pages
• 2 - 2KB CHR pages
• 3 - 1KB CHR pages

PRG RAM Protect 1 ($5102)

7  bit  0
---- ----
xxxx xxWW
       ||
       ++- RAM protect 1

In order to enable writing to PRG RAM, this must be set to '10'.

PRG RAM Protect 2 ($5103)

7  bit  0
---- ----
xxxx xxWW
       ||
       ++- RAM protect 2

In order to enable writing to PRG RAM, this must be set to '01'.

Extended RAM mode ($5104)

7  bit  0
---- ----
xxxx xxXX
       ||
       ++- Specify extended RAM usage

• 0 - Use as extra nametable (possibly for split mode)
• 1 - Use as extended attribute data OR an extra nametable
• 2 - Use as ordinary RAM
• 3 - Use as ordinary RAM, write protected

Nametable mapping ($5105)

7  bit  0
---- ----
DDCC BBAA
|||| ||||
|||| ||++- Select nametable at PPU $2000-$23FF
|||| ++--- Select nametable at PPU $2400-$27FF
||++------ Select nametable at PPU $2800-$2BFF
++-------- Select nametable at PPU $2C00-$2FFF

Nametable values:

• 0 - On-board VRAM page 0
• 1 - On-board VRAM page 1
• 2 - Internal Expansion RAM, only if the Extended RAM mode allows it ($5104 is 00/01); otherwise, the nametable will read as all zeros,
• 3 - Fill-mode data

Examples:

• $44 (01 00 01 00) - Vertical mirroring
• $50 (01 01 00 00) - Horizontal mirroring
• $14 (00 01 01 00) - Diagonal mirroring
• $00 (00 00 00 00) - 1-screen mirroring, low bank

Fill-mode tile ($5106)

7  bit  0
---- ----
TTTT TTTT
|||| ||||
++++-++++- Specify tile number to use for fill-mode nametable

Fill-mode color ($5107)

7  bit  0
---- ----
xxxx xxAA
       ||
       ++- Specify attribute bits to use for fill-mode nametable

PRG Bankswitching

PRG RAM bank ($5113)

7  bit  0
---- ----
xxxx xCBB
      |||
      |++- Select 8KB PRG RAM bank at $6000-$7FFF
      +--- Select PRG RAM chip

The MMC5 supports 2 PRG RAM chips, each up to 32KB in length.

PRG bank 0 ($5114)

7  bit  0
---- ----
RBBB BBBB
|||| ||||
|+++-++++- Bank number
+--------- RAM/ROM toggle (0: RAM; 1: ROM)

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select an 8KB PRG bank at $8000-$9FFF

When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.

PRG bank 1 ($5115)

7  bit  0
---- ----
RBBB BBBB
|||| ||||
|+++-++++- Bank number
+--------- RAM/ROM toggle (0: RAM; 1: ROM)

• Mode 0 - Ignored
• Mode 1 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
• Mode 2 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
• Mode 3 - Select an 8KB PRG bank at $A000-$BFFF

When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.

PRG bank 2 ($5116)

7  bit  0
---- ----
RBBB BBBB
|||| ||||
|+++-++++- Bank number
+--------- RAM/ROM toggle (0: RAM; 1: ROM)

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Select an 8KB PRG bank at $C000-$DFFF
• Mode 3 - Select an 8KB PRG bank at $C000-$DFFF

When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.

PRG ROM bank 3 ($5117)

7  bit  0
---- ----
xBBB BBBB
 ||| ||||
 +++-++++- PRG ROM bank number

• Mode 0 - Select a 32KB PRG ROM bank at $8000-$FFFF (ignore bottom 2 bits)
• Mode 1 - Select a 16KB PRG ROM bank at $C000-$FFFF (ignore bottom bit)
• Mode 2 - Select an 8KB PRG ROM bank at $E000-$FFFF
• Mode 3 - Select an 8KB PRG ROM bank at $E000-$FFFF

CHR Bankswitching

Registers $5120-$5127 apply to sprite graphics and $5128-$512B for background graphics, but ONLY when 8x16 sprites are enabled.

Otherwise, the last set of registers written to (either $5120-$5127 or $5128-$512B) will be used for all graphics.

Sprite CHR bank 0 ($5120)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR bank at PPU $0000-$03FF

Sprite CHR bank 1 ($5121)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Select a 2KB CHR bank at PPU $0000-$07FF
• Mode 3 - Select a 1KB CHR bank at PPU $0400-$07FF

Sprite CHR bank 2 ($5122)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR bank at PPU $0800-$0BFF

Sprite CHR bank 3 ($5123)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Select a 4KB CHR ROM bank at PPU $0000-$0FFF
• Mode 2 - Select a 2KB CHR ROM bank at PPU $0800-$0FFF
• Mode 3 - Select a 1KB CHR ROM bank at PPU $0C00-$0FFF

Sprite CHR bank 4 ($5124)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR ROM bank at PPU $1000-$13FF

Sprite CHR bank 5 ($5125)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Select a 2KB CHR ROM bank at PPU $1000-$17FF
• Mode 3 - Select a 1KB CHR ROM bank at PPU $1400-$17FF

Sprite CHR bank 6 ($5126)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR ROM bank at PPU $1800-$1BFF

Sprite CHR bank 7 ($5127)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Select an 8KB CHR ROM bank at PPU $0000-$1FFF
• Mode 1 - Select a 4KB CHR ROM bank at PPU $1000-$1FFF
• Mode 2 - Select a 2KB CHR ROM bank at PPU $1800-$1FFF
• Mode 3 - Select a 1KB CHR ROM bank at PPU $1C00-$1FFF

Background CHR bank 0 ($5128)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR ROM bank at PPU $0000-$03FF and $1000-$13FF

Background CHR bank 1 ($5129)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Select a 2KB CHR ROM bank at PPU $0000-$07FF and $1000-$17FF
• Mode 3 - Select a 1KB CHR ROM bank at PPU $0400-$07FF and $1400-$17FF

Background CHR bank 2 ($512A)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Ignored
• Mode 1 - Ignored
• Mode 2 - Ignored
• Mode 3 - Select a 1KB CHR ROM bank at PPU $0800-$0BFF or $1800-$1BFF

Background CHR bank 3 ($512B)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Bank number

• Mode 0 - Select an 8KB CHR ROM bank at PPU $0000-$1FFF
• Mode 1 - Select a 4KB CHR ROM bank at PPU $0000-$0FFF or $1000-$1FFF
• Mode 2 - Select a 2KB CHR ROM bank at PPU $0800-$0FFF or $1800-$1FFF
• Mode 3 - Select a 1KB CHR ROM bank at PPU $0C00-$0FFF or $1C00-$1FFF

Upper CHR Bank bits ($5130)

7  bit  0
---- ----
xxxx xxBB
       ||
       ++- Upper bits for subsequent CHR bank writes

When the MMC5 is using 2KB/1KB CHR banks, only 512KB/256KB of CHR ROM can be selected using the previous registers. To access all 1024KB in those modes, first write the upper bit(s) to register $5130 and then write the lower bits to $5120-$512B. When the Extended RAM mode is set to 1, this selects which 256KB of CHR ROM is to be used for all background tiles on the screen.

Other Registers

Vertical Split Mode ($5200)

7  bit  0
---- ----
ESxW WWWW
|| | ||||
|| +-++++- Specify vertical split start/stop tile
|+-------- Specify vertical split screen side (0:left; 1:right)
+--------- Enable vertical split mode

When vertical split mode is enabled, all VRAM fetches corresponding to the appropriate screen region will be redirected to Extended RAM (as long as its mode is set to 0 or 1).

Vertical Split Scroll ($5201)

7  bit  0
---- ----
YYYY YYYY
|||| ||||
++++-++++- Specify vertical scroll value to use in split region

MMC5 boards wired in "CL" mode may only use vertical scroll values whose bottom 3 bits match the Nes PPU's fine vertical scroll value. In "SL" mode, any values can be used.

Horizontal scrolling is not allowed within the split region.

Vertical Split Bank ($5202)

7  bit  0
---- ----
BBBB BBBB
|||| ||||
++++-++++- Select a 4 KB CHR bank at $0000-$0FFF and $1000-$1FFF while rendering the split region.

IRQ Counter ($5203)

7  bit  0
---- ----
LLLL LLLL
|||| ||||
++++-++++- Specify scanline number to generate IRQ at

IRQ Status ($5204, read/write)

Write

7  bit  0
---- ----
Exxx xxxx
|
+--------- IRQ Enable flag (1=IRQs enabled)

Read

7  bit  0
---- ----
SVxx xxxx
||
|+-------- "In Frame" signal
+--------- IRQ Pending flag

When set, the "In Frame" signal specifies that the PPU is currently rendering a scanline. It also plays a role in how IRQs are generated.

The IRQ Pending flag may be raised even if IRQs are disabled.

Any time this register is read, the IRQ Pending flag is cleared (acknowledging the IRQ).

For details, see IRQ counter operation.

Multiplier ($5205, read/write)

Write

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- Specify multiplicand

Read

7  bit  0
---- ----
PPPP PPPP
|||| ||||
++++-++++- Lower 8 bits of product

Multiplier ($5206, read/write)

Write

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- Specify multiplier

Read

7  bit  0
---- ----
PPPP PPPP
|||| ||||
++++-++++- Upper 8 bits of product

Expansion RAM ($5C00-$5FFF, read/write)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- Expansion RAM data

• Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
• Mode 2 - Readable and writable
• Mode 3 - Read-only

In Mode 1, each byte of Expansion RAM is used to enhance the tile at the corresponding address in each nametable.

7  bit  0
---- ----
AACC CCCC
|||| ||||
||++-++++- Select 4 KB CHR bank to use with specified tile
++-------- Select palette to use with specified tile

IRQ Counter Operation

The MMC5 has an 8-bit incrementing IRQ counter that watches the PPU as it renders, and counts each passing scanline. When the counter reaches the desired IRQ scanline (specified by the $5203 register), it signals an IRQ. It also uses an In Frame signal which can be read from $5204.6 in conjunction with the 8-bit counter. Games can use this signal as an indication of whether or not the PPU is currently in rendering time.

The game has no direct access to the internal IRQ counter.

How the MMC5 actually detects scanlines is still unknown. One theory is that it watches for the two dummy nametable reads which occur at the end of each scanline. It appears that all 240 rendered scanlines as well as the pre-render scanline are all detected by the MMC5. It also appears that scanlines are detected near their end (or near the start of the next scanline). When a game sets the desired IRQ scanline to $04, the IRQ will occur near the start of the 5th rendered scanline.

When the MMC5 detects a scanline, the following events occur:

• if the In Frame signal is clear, set it, reset the IRQ counter to 0, and clear the IRQ Pending flag
• otherwise, increment the IRQ counter. If it now equals the IRQ scanline ($5203), raise IRQ Pending flag

Note the above logic makes it impossible for an IRQ to occur when $5203 is set to $00

The In Frame signal is cleared as soon as the MMC5 no longer detects PPU rendering. This happens at the end of the last rendered scanline, and whenever the PPU is switched off (Sprite and BG rendering disabled).

Note that there are side-effects to switching off the PPU mid frame. Clearing the In Frame signal effectively resets the IRQ counter as can be seen in the logic given above. Therefore, if the PPU is switched back on in the frame, the IRQ counter will begin counting from $00 again.

The IRQ Pending flag is raised when the desired scanline is reached regardless of whether or not IRQs are enabled. $5204.7 can still be read as set even when IRQ Enable flag is clear. However, an actual IRQ is only sent to the CPU if both the IRQ Enable flag and IRQ Pending flag are raised.

Hardware

The MMC5 exists in a 100-pin TQFP package.

At least two different versions of the MMC5 are known to exist: MMC5, and MMC5B. Their differences are unknown.