MMC3 pinout: Difference between revisions

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m (Created page with '<pre> 33 23 | | .------. 34-| |-22 | MMC3 | 44-| |-12 \------' | | 01 11 </pre> {| border=1 ! Pin || Function || Pin || Function || ...')
 
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<pre>
Nintendo MMC3: 44-pin QFP
    33  23
    |    |
  .------.
34-|      |-22
  | MMC3 |
44-|      |-12
  \------'
    |    |
    01  11
</pre>


{| border=1
                        / \
! Pin || Function || Pin || Function || Pin || Function || Pin || Function
                      / O \
|-
                ? -> /01 44\ -> CHR A16
| 01 || ??? *1 || 12 || CHR A17 || 23 || PRG A18 || 34 || CPU D0
          CHR A10 <- /02  43\ -> CHR A11
|-
        PPU A12 -> /03    42\ -> PRG RAM /WE
| 02 || CHR A10 *1 || 13 || /IRQ || 24 || CPU A13 || 35 || CPU D5
        PPU A11 -> /04      41\ -> PRG RAM +CE
|-
      PPU A10 -> /05        40\ -  GND
| 03 || PPU A12 || 14 || CPU /CE || 25 || PRG A17 || 36 || CPU D1
          GND  - /06        \ 39\ <- CPU D3
|-
    CHR A13 <- /07          \ 38\ <- CPU D2
| 04 || PPU A11 || 15 || GND *2 || 26 || PRG /CE || 37 || CPU D4
    CHR A14 <- /08        \  _\ 37\ <- CPU D4
|-
  CHR A12 <- /09        \ \|   36\ <- CPU D1
| 05 || PPU A10 || 16 || ??? *2 || 27 || VCC || 38 || CPU D2
VRAM A10 <- /10          \ \    35\ <- CPU D5
|-
CHR A15 <- /11        \  _\    o  34\ <- CPU D0
| 06 || GND || 17 || CPU R/W || 28 || GND || 39 || CPU D3
CHR A17 <- \12      /\ \|         33/ <- CPU D6
|-
    /IRQ <- \13        \ \        32/ <- CPU A0
| 07 || CHR A13 || 18 || PRG A15 || 29 || M2 || 40 || GND
  /ROMSEL -> \14  /    \        31/ <- CPU D7
|-
        GND - \15  |_  /      30/ -> PRG RAM /CE
| 08 || CHR A14 || 19 || PRG A13 || 30 || PRG RAM /CE || 41 || PRG RAM +CE
          ? -> \16  |         29/ <- M2
|-
      CPU R/W -> \17  |/      28/ -  GND
| 09 || CHR A12 || 20 || CPU A14 || 31 || CPU D7 || 42 || PRG RAM /WE
      PRG A15 <- \18         27/ - VCC
|-
        PRG A13 <- \19      26/ -> PRG /CE
| 10 || VRAM A10 || 21 || PRG A16 || 32 || CPU A0 || 43 || CHR A11
        CPU A14 -> \20     25/ -> PRG A17
|-
          PRG A16 <- \21  24/ <- CPU A13
| 11 || CHR A15 || 22 || PRG A14 || 33 || CPU D6 || 44 || CHR A16
          PRG A14 <- \22 23/ -> PRG A18
|}
                      \ O /
                        \ /
01 sometimes shorted to pin 2, otherwise floating
16 sometimes grounded, otherwise floating


*1: PINS 1 & 2.  Sometimes these are connected together. If they are not, pin 1 is left floating.
Note the orientation of the text: "MMC3" when viewed upright specifies pin 1 is bottom face, leftmost.
*2: PINS 15 & 16. Sometimes these are connected together. If they are not, pin 16 is left floating.

Revision as of 01:15, 2 July 2012

Nintendo MMC3: 44-pin QFP

                       / \
                      / O \
                ? -> /01 44\ -> CHR A16
         CHR A10 <- /02   43\ -> CHR A11
        PPU A12 -> /03     42\ -> PRG RAM /WE
       PPU A11 -> /04       41\ -> PRG RAM +CE
      PPU A10 -> /05         40\ -  GND
         GND  - /06         \ 39\ <- CPU D3
    CHR A13 <- /07           \ 38\ <- CPU D2
   CHR A14 <- /08         \  _\ 37\ <- CPU D4
  CHR A12 <- /09         \ \|    36\ <- CPU D1
VRAM A10 <- /10           \ \     35\ <- CPU D5
CHR A15 <- /11         \  _\    o  34\ <- CPU D0
CHR A17 <- \12       /\ \|         33/ <- CPU D6
    /IRQ <- \13        \ \        32/ <- CPU A0
  /ROMSEL -> \14   /    \        31/ <- CPU D7
       GND  - \15  |_   /       30/ -> PRG RAM /CE
          ? -> \16   |         29/ <- M2
     CPU R/W -> \17  |/       28/ -  GND
      PRG A15 <- \18         27/ -  VCC
       PRG A13 <- \19       26/ -> PRG /CE
        CPU A14 -> \20     25/ -> PRG A17
         PRG A16 <- \21   24/ <- CPU A13
          PRG A14 <- \22 23/ -> PRG A18
                      \ O /	 
                       \ /	 	 

01 sometimes shorted to pin 2, otherwise floating
16 sometimes grounded, otherwise floating

Note the orientation of the text: "MMC3" when viewed upright specifies pin 1 is bottom face, leftmost.