APU Triangle: Difference between revisions
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The [[APU Misc|timer | The sequencer is clocked by a [[APU Misc|timer]] whose period is the 11-bit value (<tt>%HHH.LLLLLLLL</tt>) formed by timer high and timer low, ''plus one''. | ||
So given the following: | |||
*f<sub>CPU</sub> = the [[clock rate]] of the CPU | |||
*tval = the value written to the timer high and low registers | |||
*f = the frequency of the wave generated by this channel | |||
The following relationships hold: | |||
*f = f<sub>CPU</sub>/(32*(tval + 1)) | |||
*tval = f<sub>CPU</sub>/(32*f) - 1 | |||
When the [[APU Frame Counter|frame counter]] generates a linear counter clock, the following actions occur in order: | When the [[APU Frame Counter|frame counter]] generates a linear counter clock, the following actions occur in order: | ||
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# If the control flag is clear, the halt flag is cleared. | # If the control flag is clear, the halt flag is cleared. | ||
The sequencer is clocked by the timer | The sequencer is clocked by the timer as long as both the linear counter and the [[APU Length Counter|length counter]] are nonzero. | ||
The sequencer sends the following looping 32-step sequence of values to the [[APU Mixer|mixer]]: | The sequencer sends the following looping 32-step sequence of values to the [[APU Mixer|mixer]]: | ||
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</pre> | </pre> | ||
At the lowest two [[APU Misc|timer]] periods ($400B = 0 and $400A = 0 or 1), the resulting frequency is so high that the [[APU Mixer|mixer]] effectively receives a value half way between 7 and 8. | At the lowest two [[APU Misc|timer]] periods ($400B = 0 and $400A = 0 or 1), the resulting frequency is so high (over 20 kHz) that the [[APU Mixer|mixer]] effectively receives a value half way between 7 and 8. | ||
Revision as of 14:48, 1 April 2010
The NES APU triangle channel generates a pseudo-triangle wave. It has no volume control; the waveform is either cycling or suspended. It includes a linear counter, an extra duration timer of higher accuracy than the length counter.
The triangle channel contains the following: timer, linear counter, length counter, halt flag, sequencer. The linear counter contains an internal halt flag and counter.
Linear Counter Length Counter
| |
v v
Timer ---> Gate ----------> Gate ---> Sequencer ---> (to mixer)
| $4008 | CRRR.RRRR | Linear counter setup (write) |
| bit 7 | C---.---- | Control flag (this bit is also the length counter halt flag) |
| bits 6-0 | -RRR RRRR | Counter reload value |
| $400A | LLLL.LLLL | Timer low (write) |
| bits 7-0 | LLLL LLLL | Timer low 8 bits |
| $400B | llll.lHHH | Length counter load and timer high (write) |
| bits 2-0 | ---- -HHH | Timer high 3 bits |
| Side effects | Sets the halt flag | |
The sequencer is clocked by a timer whose period is the 11-bit value (%HHH.LLLLLLLL) formed by timer high and timer low, plus one. So given the following:
- fCPU = the clock rate of the CPU
- tval = the value written to the timer high and low registers
- f = the frequency of the wave generated by this channel
The following relationships hold:
- f = fCPU/(32*(tval + 1))
- tval = fCPU/(32*f) - 1
When the frame counter generates a linear counter clock, the following actions occur in order:
- If the halt flag is set, the linear counter is reloaded with the counter reload value, otherwise if the linear counter is non-zero, it is decremented.
- If the control flag is clear, the halt flag is cleared.
The sequencer is clocked by the timer as long as both the linear counter and the length counter are nonzero.
The sequencer sends the following looping 32-step sequence of values to the mixer:
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
At the lowest two timer periods ($400B = 0 and $400A = 0 or 1), the resulting frequency is so high (over 20 kHz) that the mixer effectively receives a value half way between 7 and 8.
