INES Mapper 237: Difference between revisions
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[[Category:iNES Mappers]][[Category:Pirate multicarts]] | [[Category:iNES Mappers]][[Category:Pirate multicarts]] | ||
[[iNES Mapper 237]] represents the Teletubbies 420-in-1 multicart. | [[iNES Mapper 237]] represents the Teletubbies 420-in-1 multicart. | ||
No bus conflicts on writes: | |||
address data | |||
15 12 8 4 0 7 bit 0 | |||
---- ---- ---- ---- ---- ---- | |||
1... .... .... .BLT mtMB Bbbb | |||
||| |||| |||| | |||
||| |||| |+++-- inner 16 KiB bank | |||
+-------+-+----- outer 128 KiB bank | |||
|| ||+-------- mirroring (0:horizontal/A11 1:vertical/A10) | |||
|| |+--------- transparency (0:PRG A14 is connected to lsb of latch 1:PRG A14 is connected to CPU A14 ) | |||
|| +---------- mode (0:UNROM-PRG A14..A16 is bbb ORed with CPU A14 1:NROM-PRG A14..A16 is bbb ) | |||
|+------------- type (0:normal execution 1:PRG A0 is always 1-CPU must execute from RAM or code must be written very carefully) | |||
+-------------- lock (0:allow further writes 1:only writes to bbb are allowed | |||
The <tt>mt</tt> bits interact, so it might be more convenient to think of them together: | |||
00 - 128 KiB UNROM | |||
40 - defective interaction; UNROM but the lsb of the latch is ignored and treated as 0 | |||
80 - 16 KiB NROM (PRG A14 is connected to lsb of latch) | |||
C0 - 32 KiB NROM (PRG A14 is connected to CPU A14) | |||
See also: | See also: | ||
* http://forums.nesdev.org/viewtopic.php?f=3&t=5977 | * http://forums.nesdev.org/viewtopic.php?f=3&t=5977 | ||
* http://bootgod.dyndns.org:7777/downloads/420IN1.TXT | * http://bootgod.dyndns.org:7777/downloads/420IN1.TXT |
Revision as of 07:08, 9 May 2014
iNES Mapper 237 represents the Teletubbies 420-in-1 multicart.
No bus conflicts on writes:
address data 15 12 8 4 0 7 bit 0 ---- ---- ---- ---- ---- ---- 1... .... .... .BLT mtMB Bbbb ||| |||| |||| ||| |||| |+++-- inner 16 KiB bank +-------+-+----- outer 128 KiB bank || ||+-------- mirroring (0:horizontal/A11 1:vertical/A10) || |+--------- transparency (0:PRG A14 is connected to lsb of latch 1:PRG A14 is connected to CPU A14 ) || +---------- mode (0:UNROM-PRG A14..A16 is bbb ORed with CPU A14 1:NROM-PRG A14..A16 is bbb ) |+------------- type (0:normal execution 1:PRG A0 is always 1-CPU must execute from RAM or code must be written very carefully) +-------------- lock (0:allow further writes 1:only writes to bbb are allowed
The mt bits interact, so it might be more convenient to think of them together:
00 - 128 KiB UNROM 40 - defective interaction; UNROM but the lsb of the latch is ignored and treated as 0 80 - 16 KiB NROM (PRG A14 is connected to lsb of latch) C0 - 32 KiB NROM (PRG A14 is connected to CPU A14)
See also: