INES Mapper 113: Difference between revisions
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[[Category:iNES Mappers | {{DEFAULTSORT:113}}[[Category:iNES Mappers]][[Category:GNROM-like mappers]][[Category:Mappers using $4020-$5FFF]][[Category:Multicart mappers]] | ||
[[iNES Mapper 113]] is used to designate a multicart made for a bunch of [[NINA-003-006|NINA-03/06]] games. The | [[iNES Mapper 113]] is used to designate a multicart made for a bunch of [[NINA-003-006|NINA-03/06]] games. The board name of these larger multicarts is unknown, as none are in NesCartDB. | ||
Example Games: | |||
* ''HES 6-in-1'' | |||
* ''Mind Blower Pak'' | |||
* ''Total Funpak'' | |||
== Banks == | |||
* CPU $8000-$FFFF: 32 KB switchable PRG ROM bank (max 256 KB) | |||
* PPU $0000-$1FFF: 8 KB switchable CHR ROM bank (max 128 KB) | |||
== Registers == | |||
=== Control Register === | |||
This register is located at addresses: | |||
F bit 0 | |||
---- ---- ---- ---- | |||
010x xxx1 xxxx xxxx | |||
That is, $4100-$41FF, $4300-$43FF, $45xx, $47xx, ..., $5Dxx, and $5Fxx. | |||
7 bit 0 | |||
---- ---- | |||
MCPP PCCC | |||
|||| |||| | |||
|+||-|+++-- Select 8 KB CHR ROM bank for PPU $0000-$1FFF | |||
| ++-+----- Select 32 KB PRG ROM bank for CPU $8000-$FFFF | |||
+---------- Mirroring control (0 = Horizontal, 1 = Vertical) | |||
Note the high bit of the CHR select is shifted away from the others. | |||
== Variants == | |||
This mapper extends the [[NINA-003-006|NINA-03/06]] with an extra 4 bits of control register. The low 4 bits written behave the same, but the high 4 bits add [[mirroring]] control, 1 extra bit of CHR select, and 2 extra bits of PRG select. | |||
== References == | |||
* [http://www.romhacking.net/documents/362/ NES mapper list by Disch] |
Revision as of 18:31, 7 June 2015
iNES Mapper 113 is used to designate a multicart made for a bunch of NINA-03/06 games. The board name of these larger multicarts is unknown, as none are in NesCartDB.
Example Games:
- HES 6-in-1
- Mind Blower Pak
- Total Funpak
Banks
- CPU $8000-$FFFF: 32 KB switchable PRG ROM bank (max 256 KB)
- PPU $0000-$1FFF: 8 KB switchable CHR ROM bank (max 128 KB)
Registers
Control Register
This register is located at addresses:
F bit 0 ---- ---- ---- ---- 010x xxx1 xxxx xxxx
That is, $4100-$41FF, $4300-$43FF, $45xx, $47xx, ..., $5Dxx, and $5Fxx.
7 bit 0 ---- ---- MCPP PCCC |||| |||| |+||-|+++-- Select 8 KB CHR ROM bank for PPU $0000-$1FFF | ++-+----- Select 32 KB PRG ROM bank for CPU $8000-$FFFF +---------- Mirroring control (0 = Horizontal, 1 = Vertical)
Note the high bit of the CHR select is shifted away from the others.
Variants
This mapper extends the NINA-03/06 with an extra 4 bits of control register. The low 4 bits written behave the same, but the high 4 bits add mirroring control, 1 extra bit of CHR select, and 2 extra bits of PRG select.