INES Mapper 067

iNES Mapper 067 represents the Sunsoft-3 mapper, used in Fantasy Zone II (J).

Registers

CHR bank 0 ($8800)

The value written here selects a 2 KiB CHR ROM bank at PPU $0000-$07FF.

CHR bank 1 ($9800)

The value written here selects a 2 KiB CHR ROM bank at PPU $0800-$0FFF.

CHR bank 2 ($A800)

The value written here selects a 2 KiB CHR ROM bank at PPU $1000-$17FF.

CHR bank 3 ($B800)

The value written here selects a 2 KiB CHR ROM bank at PPU $1800-$1FFF.

IRQ load ($C800, write twice)

Write the high then low byte of a 16-bit CPU cycle count, much like PPUADDR. This directly affects the current count, not a reload value.

IRQ enable ($D800)

7  bit  0
...P ....
   |
   +------ 0: Pause counter; 1: Count

While bit 4 is true, the 16-bit count decreases by 1 every CPU cycle. Whenever the count wraps from $0000 to $FFFF, the mapper asserts an IRQ and pauses itself. Writes also acknowledge IRQ and reset a latch such that the next $C800 write goes to the high byte of the count.

Mirroring ($E800)

7  bit  0
.... ..MM
       ||
       ++- Nametable mirroring (0=vertical, 1=horizontal, 2=1scA, 3=1scB)
            aka connect VRAM A10 to (0=PPU A10, 1=PPU A11, 2=Gnd, 3=Vcc)

PRG bank ($F800)

The value written here selects a 16 KiB CHR ROM bank at CPU $8000-$BFFF. As in mapper 2, $C000-$FFFF is fixed to the last bank of PRG ROM.

 Here are Disch's original notes:  
 ========================
 =  Mapper 067          =
 ========================
 
 
 Example Games:
 --------------------------
 Fantasy Zone 2 (J)
 Mito Koumon - Sekai Manyuu Ki
 
 
 Registers:
 ---------------------------
 
 Range,Mask:   $8000-FFFF, $F800
 
   $8800:  CHR Reg 0  (2k @ $0000)
   $9800:  CHR Reg 1  (2k @ $0800)
   $A800:  CHR Reg 2  (2k @ $1000)
   $B800:  CHR Reg 3  (2k @ $1800)
 
   $C800:  IRQ Load (write twice)
   $D800:  [...E ....]  IRQ Enable (0=disabled, 1=enabled)
 
   $E800:  [.... ..MM]  Mirroring
     %00 = Vert
     %01 = Horz
     %10 = 1ScA
     %11 = 1ScB
 
   $F800:  PRG Reg  (16k @ $8000)
 
 
 
 CHR Setup:
 ---------------------------
 
       $0000   $0400   $0800   $0C00   $1000   $1400   $1800   $1C00 
     +---------------+---------------+---------------+---------------+
     |     $8800     |     $9800     |     $A800     |     $B800     |
     +---------------+---------------+---------------+---------------+
 
 
 PRG Setup:
 ---------------------------
 
       $8000   $A000   $C000   $E000  
     +---------------+---------------+
     |     $F800     |     { -1}     |
     +---------------+---------------+
 
 
 
 IRQ Operation:
 ---------------------------
 
   $C800 is a write-twice register (similar to $2005 and $2006).  The first write sets the *high* 8 bits of the
 IRQ counter, and the second write sets the *low* 8 bits.  This directly changes the actual IRQ counter -- not
 a reload value.
 
   Any write to $D800 will acknowledge the IRQ, and will also reset the toggle so that the next write to
 $C800 will be the first write.  $D800, of course, also enables/disables IRQs (bit 4).
 
   The IRQ counter, when enabled, counts down every CPU cycle.  When it wraps ($0000->FFFF), it disables
 itself and triggers an IRQ.