CPU variants

Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:

RP2A03	M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. APU Frame Counter not restarted on reset. Has broken and disabled programmable interval timer on-die. Pin 30 connects to nothing. Other differences?
RP2A03E	Pin 30 may connect to 6502 /RDY input.
RP2A03G	Reference model. Pin 30 enables a CPU test mode. Later runs introduced a DMC DMA bug [2].
RP2A03H	No known differences from late RP2A03G.
RP2A04	Not actually a CPU at all, just a jumper in a 40-pin PDIP
RP2A07	Input clock divider is 16. M2 duty cycle is 19/32 [3]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Pin 30 connects to 6502 /RDY input.
RP2A07A	no known differences relative to 2A07letterless
MG-N-501	Unlike early UA6527, DMC works
MG-P-501	Micro Genius-made clone. Die has the same (UMC) © Ⓜ B6167F marking as a UA6527P.
UA6527	UMC-made clone of 2A03G. Has swapped pulse channel duty cycles.
UA6527P	UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527. Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [4]. Additionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles) One revision has (UMC) © Ⓜ B6167F 1989 09 on the die. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for DMC DMA implicit-stop glitches (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle. Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider Runs hot. Revisions with "-" in the date stamp have a ÷15 CPU divider Runs cooler
UA6540	UMC-made clone of 2A07 [5]. Has swapped pulse duty cycles. Subsequent research implies this is identical to the early 6527P - NTSC tuning tables, ÷16 CPU divider. [6]
UM6557	Believed to be a 100% duplicate of UA6527, for use in SECAM regions.
UM6561xx-1	NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known. Earlier revisions (which?) CPU half believed identical to UA6527; later revisions correct pulse channel duties.
UM6561xx-2	NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known. Earlier revisions (which?) CPU half believed identical to UA6527P; later revisions correct pulse channel duties. F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. AF revision observed to have incorrect ASR #imm ($4B) behavior, but other stable illegal instructions work properly.
T1818	??-made NES-on-a-chip, NTSC timing. Believed to exist, but evidence currently scant.
T1818P	??-made NES-on-a-chip[[7]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
TA-03N	??-made clone of 2A03G. Pin 30 selects input clock divider?
TA-03NP	??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15? But not this one, this input clock divider is 12.
TA-03NP1	??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
PM03	Gradiente-made clone of 2A03G. [8]
GS870007	(Goldstar??)-made clone of 2A03 - has functioning decimal mode? [9]
KC-6005	Found in MT777-DX famiclone, behaves exactly like UA6527P
6005B
2011
“2A03E”	Both with and without USC insignia
KP2B03E

If you know of other differences or other revisions, please add them!

See also

• https://forums.nesdev.org/viewtopic.php?p=45889#p45889